| Patch substrate for external connection -> Monitor Keywords |
|
|
 
Patch substrate for external connectionRelated Patent Categories: Metal Working, Method Of Mechanical Manufacture, Electrical Device Making, Conductor Or Circuit Manufacturing, On Flat Or Curved Insulated Base, E.g., Printed Circuit, Etc., Manufacturing Circuit On Or In Base, By Forming Conductive Walled Aperture In BasePatch substrate for external connection description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20060191134, Patch substrate for external connection. Brief Patent Description - Full Patent Description - Patent Application Claims
CROSS-REFERENCE TO RELATED APPLICATION [0001] This application is a divisional of co-pending U.S. patent application Ser. No. 10/881,243, filed Jun. 29, 2004. BACKGROUND [0002] 1. Field [0003] Electronic device connectors and attachments, and the manufacture and connection thereof. [0004] 2. Background [0005] Electronic devices having a field or array of contacts are typically connected to other devices having similar contacts such as a printed circuit board (PCB), "board", or a "motherboard" using molded socket devices, spring clip devices, solder bumps, solder, conductive or nonconductive paste or adhesive, or by other mechanical connector devices or means. One goal of such connector devices or means is generally to provide sufficient physical connection between two devices, such as to resist physical separation of the devices or damage to the devices due to vibration, shock, or thermal factors. Another goal is to cause the fields or arrays of contacts of the devices to individually contact or register with each other, such as to form an electrically conductive connection between the electronics of the devices. In fact, sometimes it is necessary to permanently connect the contacts of a device to another device or board. For example, solder bumps may be used to connect a land grid array (LGA) of a packaging substrate, such as a substrate including a semiconductor active device, processor, or other integrated circuit, to a printed circuit board (PCB), such as a "motherboard" of a computer. The use of solder bump connections typically requires that the packaging substrate and PCB use contacts (or contact pads) having a sufficient surface area, thickness, and spacing therebetween necessary for the solder bumps to form the desired connections between the contacts of the packaging substrate and the contacts of the PBA. Selecting contacts to use may take into consideration the amount of solder and heat necessary to cause the solder bumps to form the desired connections between the contacts of the packaging substrate and the contacts of the PBA. Moreover, selecting contacts to use and wiring or conductive traces to the contacts may take into consideration the amount of solder and heat necessary to cause the solder bumps to form the desired connections between the contacts of the packaging substrate and the contacts of the PBA. BRIEF DESCRIPTION OF THE DRAWINGS [0006] Various features, aspects and advantages will become more thoroughly apparent from the following detailed description, the set of claims, and accompanying drawings in which: [0007] FIG. 1 is a top perspective view of a land grid array (LGA) of contacts. [0008] FIG. 2 is a cross-sectional view of a patch substrate having electrical connections running between external connection pads on one side and plated contacts on the other side, and of the patch substrate electrically connecting an LGA of contacts of a first electrical device to an LGA of contacts of a second electrical device. [0009] FIG. 3 is a top perspective partial cut away view of electrically conductive traces to electrical contacts of an LGA of an electrical device. [0010] FIG. 4 is a cross-sectional view of a patch substrate attached to a packaging placer for placing the patch substrate on a first electrical device. [0011] FIG. 5 is a cross-sectional view of a patch substrate being attached to a first electrical device by a packaging placer. [0012] FIG. 6 is a cross-sectional view of a patch substrate attached to a first electrical device and having metal plates electronically coupled to contacts of the first electrical device. [0013] FIG. 7 is a cross-sectional view of a second electrical device attached to and electronically coupled to a patch substrate, and the patch substrate attached to and electronically coupled to a first electronic device. [0014] FIG. 8 is a cross-sectional view of a patch substrate having a core material, a layer of foil on the core material, and a hole in the core material. [0015] FIG. 9 is the patch substrate of FIG. 8 with a capped electronically conductive material in the hole and portions of the foil removed. [0016] FIG. 10 is the patch substrate of FIG. 9 laminated with an electronically insulating adhesive. [0017] FIG. 11 is the patch substrate of FIG. 10 attached to a first electronic device with the cured adhesive and having metal plates thermo-compression bonded to contacts of the first electronic device. DETAILED DESCRIPTION [0018] FIG. 1 is a top perspective view of a land grid array (LGA) of contacts. FIG. 1 shows electronic device 30 having land grid array (LGA) 70 of contacts, with contacts extending along rows A through U, and along columns 1 through 17, excluding center portion 71. It is contemplated that device 30 may be (e.g., such as where LGA 70 is an LGA of) a printed circuit board (PCB), an electronic component "board", a socket, a "motherboard", a video card, a processor, a post processor, a video processor, a memory board, a digital signal processor, a board with a power transformer connection on the board, a board with a device on/off power switch connection on the board. It is also contemplated that device 30 may be (e.g., such as where LGA 70 is an LGA of) a packaging substrate, such as a substrate having (or attached to) an electronic active device, a silicon electronic component, an active silicon device, an integrated circuit, a chip, a memory, a processor, a digital signal processor, a post processor, a video processor, a memory chip, a central processing unit (CPU), etc. [0019] FIG. 1 shows LGA 70 having five rows and five columns of contacts between the outer perimeter and center space 71. Specifically, FIG. 1 shows first row R1, second row R2, third row R3, fourth row R4, and fifth row R5. FIG. 1 shows LGA 70 with a 17.times.17 array of contacts. It may be appreciated that LGA 70 may represent an array of more or less contacts, in more or fewer rows, and/or in more or fewer columns than shown in FIG. 1. Also, LGA 70 may represent and LGA with a larger or smaller center space than space 71, a different shaped array of contacts, and/or having more or fewer rows and/or columns of contacts between the outer perimeter of the LGA and the center space. [0020] According to embodiments, LGA 70 includes first contact 36 of row one R1, and each contact of LGA 70 may be a contact such as contact 36. Moreover, according to embodiments, each contact of LGA 170 may have a diameter D1 between 200 .mu.m and 400 .mu.m, such as by having a diameter of 240, 260, 280, 290, 300, 310, 320, 340, or 360 .mu.m. Also, contacts of LGA 70 may be a type of contact typically attached or electronically coupled to by a solder ball or bump. Alternatively, contacts of LGA 70 may be contacts having a diameter of between 50 .mu.m and 100 .mu.m, such as a diameter of 55, 60, 65, 70, 75, 80, 85, or 90 .mu.m. Moreover, contacts of LGA 70 may be a type of contact connected, attached, or electronically connected to a plated (or capped) contact with a tin-copper interconnection interface and/or thermo-compression bonding. Continue reading about Patch substrate for external connection... Full patent description for Patch substrate for external connection Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Patch substrate for external connection patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. Start now! - Receive info on patent apps like Patch substrate for external connection or other areas of interest. ### Previous Patent Application: Multilayer board and its manufacturing method Next Patent Application: Methods for establishing electrical connections by drawing one or both of an element of an electrical connector and a contact toward the other Industry Class: Metal working ### FreshPatents.com Support Thank you for viewing the Patch substrate for external connection patent info. IP-related news and info Results in 0.14057 seconds Other interesting Feshpatents.com categories: Canon USA , Celera Genomics , Cephalon, Inc. , Cingular Wireless , Clorox , Colgate-Palmolive , Corning , Cymer , 174 |
 * Protect your Inventions * US Patent Office filing 
PATENT INFO |
|
