Site News  |   Monitor Keywords  |   Monitor Archive  |   Organizer  |   Account Info  |

Passive electronic device

Passive electronic device description/claims

The present invention is related to an interposer device. More specifically, the present invention is related to an interposer device which allows for direct capacitance decoupling for decreased inductance combined with electronic filtering of microprocessor feed power in a minimized device footprint.

Integrated circuits (IC) containing decoupling capacitors are commonly employed in virtually all modem electronic systems. Decoupling capacitors are typically mounted between power and ground circuits to reduce noise to the IC. For the purposes of the present invention an integrated circuit may be a discrete element or it may be incorporated into an integrated circuit package wherein the IC package comprises additional functioning elements.

The location of decoupling capacitors has become increasingly more important as the clock speed, or switching frequencies, of modem IC's has increased. With low clock speeds, such as hundreds of kilohertz to tens of megahertz, the location is of less significance. As clock speeds approach hundreds of megahertz or higher it becomes imperative to minimize the inductance of the decoupling circuit traces such that parasitic inductance is minimized. Parasitic inductance has been reduced markedly by optimization of the component design, as well as positioning of the decoupling capacitors nearer to the IC and with use of smaller capacitors having lower inductance values. As clock speeds increase further these prior improvements will be less suitable for high speed decoupling as the associated parasitic inductances associated with these methods has largely been minimized.

Capacitive interposers situated between the IC and printed circuit board (PCB) have improved the parasitic inductance as indicated in U.S. Pat. No. 6,961,231. A capacitive interposer has an array of lands on each surface. The IC, or IC package, is coupled to the interposer at the lands on one surface of the interposer. The PCB is coupled to the capacitive interposer at lands on the opposite side of the interposer. Electrically conductive vias in the capacitive interposer interconnect the lands with terminals on the opposite side. Capacitors are mounted on, or incorporated into, the capacitive interposer thereby providing the decoupling function desired.

Capacitive interposers are relatively thin and typically do not add significantly to the overall size of the electronic package. It is typical in the electronics industry that each generation of advancement in electronic devices demands higher clock speeds, smaller size and increased functionality. This ongoing demand requires even further reduction in size as well as in decreases in parasitic inductance.

It is an object of the present invention to provide improvements in capacitive interposers.

It is another object of the present invention to provide an interposer which provides power directly through capacitors thereby reducing the incidence of unwanted high frequency signals (or noise) on the power sent directly to the IC as the capacitors are configured for an electronic filtering function as well as for decoupling.

A particular feature of the present invention is the ability to increase the functionality of a capacitive interposer without an increase in the spatial footprint requirement for the IC or IC package.

These and other advantages, as will be realized, are provided in an interposer. The interposer has a first planar face and a second planar face. An array of upper connections is on the first planar face and opposing lower connections are on the second planar face with conduction paths between each upper connection of the upper connections and a lower connection of the lower connections. At least one capacitor is provided. Each capacitor has a plurality of parallel plates with a dielectric there between. At least one first external termination is in electrical contact with a first set of alternate parallel plates and at least one second external termination is in electrical contact with a second set of alternate parallel plates. Each capacitor is mounted on the first planar face with the first external termination in direct electrical contact with a first upper connection and the second external termination is in direct electrical contact with a second upper connection. At least one upper connection, first external termination and second external termination are arranged for direct electrical contact with element contact pads of a common element.

Yet another embodiment is provided in an electronic package. The electronic package has an integrated circuit with an array of IC contacts, a printed circuit board with an array of PCB contacts and an interposer between the integrated circuit and the printed circuit board. The interposer has a first planar face and a second planar face. An array of upper connections is on the first planar face and opposing lower connections are on the second planar face with conduction paths between each upper connection of the upper connections and a lower connection of the lower connections. At least one capacitor is provided. Each capacitor has a plurality of parallel plates with a dielectric there between. At least one first external termination is in electrical contact with a first set of alternate parallel plates and at least one second external termination is in electrical contact with a second set of alternate parallel plates. The capacitor is mounted on the first planar face with the first external termination in direct electrical contact with a first upper connection and the second external termination is in direct electrical contact with a second upper connection. At least one upper connection, first external termination and second external termination are in direct electrical contact with one of the array of IC contacts and the array of the PCB contacts. The lower connections are in electrical contact with one of the array of IC contacts and the array of PCB contacts different from the upper connections.

Yet another embodiment is provided in an electronic device. The electronic device has an electronic package with an integrated circuit having an array of IC contacts, at least one printed circuit board with an array of PCB contacts and an interposer between the integrated circuit and the printed circuit board. The interposer has a first planar face and a second planar face. An array of upper connections is on the first planar face and opposing lower connections are on the second planar face with conduction paths between each upper connection of the upper connections and lower connection of the lower connections. At least one capacitor is provided. The capacitor has a plurality of parallel plates with a dielectric there between. At least one first external termination is in electrical contact with a first set of alternate parallel plates. At least one second external termination is in electrical contact with a second set of alternate parallel plates. The capacitor is mounted on the first planar face with the first external termination in direct electrical contact with a first upper connection and the second external termination is in direct electrical contact with a second upper connection. At least one upper connection, the first external termination and the second external termination are in direct electrical contact with one of the array of IC contacts and the array of PCB contacts. The lower contact pads are in electrical contact with one of the array of IC contacts and the array of PCB contacts different from the upper connections. A power supply is provided for supplying power to the electronic package. An input device is provided which is capable of interfacing to provide an input signal to the electronic package. An output device is provided for sending an output signal from the electronic package.

FIG. 1 is a cross-sectional schematic representation of an embodiment of the present invention.

FIG. 2 is a front view schematic representation of an embodiment of the present invention.

FIG. 3 is a cross-sectional view taken along line 3-3 of FIG. 2.

FIG. 4 is a partial cross-sectional schematic view of an embodiment of the present invention.

FIG. 5 is a front view schematic representation of an embodiment of the present invention.

• Provisional Patent
• Utility Patent

• What Is a Patent?
• What Is a Trademark or Servicemark?
• What Is a Copyright?
• Patent Laws