| Parallel equalizer for ds-cdma uwb system and method thereof -> Monitor Keywords |
|
|
 
Parallel equalizer for ds-cdma uwb system and method thereofRelated Patent Categories: Pulse Or Digital Communications, Equalizers, Automatic, AdaptiveParallel equalizer for ds-cdma uwb system and method thereof description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20070133670, Parallel equalizer for ds-cdma uwb system and method thereof. Brief Patent Description - Full Patent Description - Patent Application Claims
FIELD OF THE INVENTION [0001] The present invention relates to a parallel equalizer for a direct sequence-code division multiple access (DS-CDMA) ultra wide-band (UWB) system and a method thereof; and, more particularly, to a parallel equalizer for a DS-CDMA UWB system and method thereof which updates filter tap coefficients based on a weight update block (WUB) and estimates transmission symbols in L filter blocks (FB), different from updating the filter tap coefficients of L WUBs individually in the conventional parallel equalizer to thereby decrease a complexity and a power consumption of the parallel equalizer. DESCRIPTION OF RELATED ART [0002] A direct sequence-code division multiple access (DS-CDMA) ultra wide-band (UWB) system transmits signals by using an ultra wide-band frequency. Therefore, a serious synchronous error of the signals by a multi-path fading and a phase offset occurred by a multi-path of transmission channel, and a frequency offset occurring between clocks used in a radio frequency (RF) transceiver are generated when the signals are transmitted. [0003] To solve the serious synchronous error, a module for setting a packet synchronization and a symbol synchronization is designed and a channel estimator and a rake receiver for dealing with a channel variation during data frame transmission period are used for recovering a transmission data in a receiving block. [0004] However, delay of the multi-path fading is equal to or more than 150 to 200 nsec in a UWB channel environment. Since an inter-symbol interference (ISI) occurred in data transition cannot be removed by only the rake receiver, performance of a DS-CDMA UWB modem receiver is dropped. Therefore, an equalizer should be employed to a receiving unit of the DS-CDMA UWB modem for overcoming the above problems. [0005] In a data frame structure of the DS-CDMA UWB modem, a normal preamble is allocated with 15 .mu.s. Herein, an allocated duration for converging filter tap coefficients of the equalizer by using a training symbol in order to remove the ISI is between 10 .mu.s and 15 .mu.s after transmitting a first preamble sequence. Since convergence of the equalizer by using the training symbol and processing of high-speed data should be performed within the duration of preamble transmitting in the UWB system, the equalizer of the receiving block is needed to be designed as a parallel processing structure. [0006] Generally, the filter tap coefficients of a symbol rate linear equalizer (SRLE) performing a parallel processing are adapted by a least mean-square algorithm. The least mean-square algorithm updates the filter tap coefficients in an opposition direction of a noisy error gradient. An adaptation (optimization) of the l.sup.th filter tap coefficients of the equalizer is expressed by the following Eq. 1. c.sub.n+1,l =c.sub.n,l+.DELTA..sub.ffe.sub.n,l, l=0,1, . . . , L-1 Eq. 1 [0007] Herein, an error rate e.sub.n,l corresponds to S.sub.n-1-c.sub.n,l.sup.Tr.sub.n,l; S.sub.n-132 S.sub.n-1-d is an output of the slicer at the n.sup.th symbol period; d denotes a overall delay from the transmitter to the receiver in baud rate interval. .DELTA..sub.ff is a step size, and the symbol ().sup.T is a transpose of (). [0008] The real vector of the l.sup.th filter tap coefficients of the equalizer c.sub.n,l.sup.T and the real vector of an l.sup.th input signal of the equalizer r.sub.n,l.sup.T are expressed by the following Eq. 2. c.sub.n,l.sup.T=[c.sub.n,l,0 c.sub.n,l,1 . . . c.sub.n,l,N-1]r.sub.n,l.sup.T=[r.sub.n-l r.sub.n-4-l . . . r.sub.n-4 (N-1)-l] Eq. 2 [0009] Herein, N is the number of the filter tap coefficients of the SRLE. [0010] FIG. 1 is a diagram of a general receiver of DS-CDMA UWB modem. [0011] The receiver of DS-CDMA UWB modem (hereinafter, which is referred to as DS-CDMA UWB modem receiver) includes an analog/digital converter (ADC) 10, a correlator 11, a rake receiver 12, a parallel equalizer (an L-parallel equalizer) 13 and a viterbi decoder 14. [0012] A RF processing block (not shown in FIG. 1) of the DS-CDMA UWB modem receiver receives an RF transmission signal from a transmitter, converts the RF transmission signal into an analog baseband signal and transmits the analog baseband signal to the ADC 10. [0013] The ADC 10 receives and converts the analog baseband signal 101 into a digital signal 102 (M digital signals). The correlator 11 receives the M digital signals 102 from the ADC 10, performs correlation detection operation for the M digital signals and outputs M result signals (complex correlation signal) 103 into the rake receiver 12. [0014] The rake receiver 12 receives the M complex correlation signals from the correlator 11 and outputs L real symbol signals 104 into the parallel equalizer 13. The parallel equalizer 13 receives the L real symbol signals, eliminates the ISI and outputs L symbol decision signals 105. [0015] Then, the viterbi decoder 14 receives the L symbol decision signals from the parallel equalizer 13 and obtains an encoding gain. Herein, the viterbi decoder 14 which is a decoder designed in the receiver based on a convolution encoder of the transmitter having L' outputs signals 106 (M>L>L'). [0016] FIG. 2 is a detailed diagram illustrating a conventional parallel equalizer and represents the L-parallel equalizer 13 applied to the DS-CDMA UWB modem receiver generally. [0017] As shown in FIG. 2, each equalizer (equalizing block) of the L-parallel equalizer 13 used in the DS-CDMA UWB modem receiver includes a weight update block (WUB) 24, a delaying block 21, a filter block (FB) 22 and a symbol decision block 23. [0018] The WUB updates the filter tap coefficients by using an input signal of the equalizer and a symbol error extracted in the slicer. The delaying block 21 delays the input signal of the equalizer and obtains N signals used in the FB 22 and the WUB 24. Herein, the delaying block 21 is presented as separate block, but the delaying block 21 may be included in the FB 22 and the WUB 24. [0019] The FB 22 obtains a symbol decision signal by using the updated filter tap coefficients from the WUB 24 and the input signal of the equalizer. The symbol decision block 23 decides a transmission symbol based on a result from the FB 22 or obtains the symbol error. [0020] Among the L input signals of equalizer outputted from the rake receiver 12, a first input signal r.sub.n 201 is used as a input signal of a first FB; a second input signal r.sub.n-1 205 is used as a input signal of a second FB; a L.sup.th input signal r.sub.n-(L-1) 207 is used as a input signal of a L.sup.th FB. [0021] The conventional parallel equalizer is formed by L equalizing blocks having same structure. A first equalizing block will be described as below and L-1 numbers of equalizing blocks are designed as the same as the first equalizing block. [0022] As shown in FIG. 2, the N input values (r.sub.n, r.sub.n-L, . . . , r.sub.n-L(N-1)) used in the FB 22 and the WUB 24 are generated by passing the input signal of equalizer r.sub.n through N-1 D flip-flops 240 to 242. Continue reading about Parallel equalizer for ds-cdma uwb system and method thereof... Full patent description for Parallel equalizer for ds-cdma uwb system and method thereof Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Parallel equalizer for ds-cdma uwb system and method thereof patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. Start now! - Receive info on patent apps like Parallel equalizer for ds-cdma uwb system and method thereof or other areas of interest. ### Previous Patent Application: Method and system for equalization of a replacement load Next Patent Application: Active delay line Industry Class: Pulse or digital communications ### FreshPatents.com Support Thank you for viewing the Parallel equalizer for ds-cdma uwb system and method thereof patent info. IP-related news and info Results in 0.35195 seconds Other interesting Feshpatents.com categories: Novartis , Pfizer , Philips , Polaroid , Procter & Gamble , 174 |
 * Protect your Inventions * US Patent Office filing 
PATENT INFO |
|
