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Pad structure for bonding pad and probe pad and manufacturing method thereofRelated Patent Categories: Active Solid-state Devices (e.g., Transistors, Solid-state Diodes), Combined With Electrical Contact Or Lead, Die BondPad structure for bonding pad and probe pad and manufacturing method thereof description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20070187838, Pad structure for bonding pad and probe pad and manufacturing method thereof. Brief Patent Description - Full Patent Description - Patent Application Claims
FIELD OF THE INVENTION [0001] The present invention relates to an integrated circuit device structure, and more particularly to a mark-shaped pad structure for a bonding pad and a probe pad. BACKGROUND OF THE INVENTION [0002] After integrated circuits are formed on a semiconductor wafer, the top metal layer is defined as a plurality of bonding pads to form a multi-layered wiring with the metal lines below. The wafer is then cut into dies for further IC chip electronic packaging. [0003] In the electronic packaging of an IC chip, the dies cut from the wafer are bonded to a lead frame with a bonder, and the bonding pads on the IC chip are electrically connected with corresponding electrical leads on the lead frame by wire bonding. In other words, the bonding pads on IC chips are the interface between the integrated circuits on the semiconductor substrate and the packaging leads on the lead frame to connect electrical signals. The electrical signals can be power signals, ground signals, and/or input/output signals. [0004] Conventionally, the active devices, e.g., MOS transistors or resistances, are laid on the central area (active area) of an IC chip and bonding pads are disposed around the active area to protect the active devices on the active area from damage during wire bonding. In some cases, bonding pads are laid on the central area of IC chip and active devices are disposed around the bonding pads for the same reason. [0005] The conventional shape of a bonding pad is a square or a rectangle. FIG. 1 shows a conventional die array on a wafer. There are scribe lines 16 on a wafer 10 to define several die areas, e.g. 12A and 12B, and the wafer 10 is cut into dies along the scribe lines 16. There are alignment markers (e.g. 14A-14C) disposed at corners of the die areas 12A and 12B on the scribe lines 16 for cutting alignment. For the intact die area 12A, the dicing machine cuts the die area 12A from the wafer 10 by aligning with the markers 14A and 14B which are disposed along the diagonal line of area 12A. However, for the fragmental die area 12B, there is no corresponding diagonal markers on scribe lines for alignment, and therefore, there is difficulty cutting die area 12B. [0006] FIGS. 2A and 2B show a conventional design of bonding pads. In FIG. 2A, the rectangular bonding pads 22A with equal size are disposed along the two longer sides of the rectangular chip 20A which is cut from a wafer. Another bonding pad design is shown in FIG. 2B. The rectangular bonding pads 22B with equal size are disposed on the central area of the rectangular chip 20B which is also cut from a wafer. The electrical layout in the chip 20A or 20B is predetermined and the bonding pads 22A or 22D on the IC chip 20A or 20B respectively are wire bonded with corresponding electrical leads on a lead frame according to the interior layout. However, it is hard to identify the bonding orientation of a chip and the leads on a lead frame because the IC chips 20A and 20B are rectangular and the bonding pads 22A and 22B are disposed on the IC chips 20A and 20B symmetrically. [0007] The same orientation problem occurs on probe pads. The probe pads are disposed in certain positions on a circuit for in-line monitoring or checking the electrical performance of the circuit design. FIG. 3 shows the conventional design for probe pads. There are several tiny probe pads 36 disposed in a certain circuit 34 on IC chip 30. The inspector measures the probe pads 36 on the circuit 34 by using a micro-probe under a microscope to obtain the electrical data. [0008] Since the square-shaped probe pads on the circuit are very tiny (e.g., 5.times.5 .mu.m), it is hard and time consuming for an inspector to identify the layout orientation between the probe pads 36 on the circuit 34 under a microscope. SUMMARY OF THE INVENTION [0009] One object of the present invention is to provide a bonding structure which is used as an orientation marker for wire bonding and a manufacturing method thereof. [0010] Another object of the present invention is to provide a bonding pad structure which can be an alignment marker for wafer dicing. [0011] Still another object of the present invention is to provide a mark-shaped pad structure for probe pads as position markers to identify the orientation of the checking circuits. [0012] To achieve the above-mentioned object, the present invention provides a bonding pad structure disposed on the surface of a semiconductor substrate with a circuit therein and a manufacturing method thereof. The structure comprises a bottom metal layer disposed over the surface of the semiconductor substrate to connect the circuit electrically, an inter-metal dielectric layer disposed over the bottom metal layer, a plurality of metal plugs formed therein to connect with the bottom metal layer below, a top metal layer disposed over the inter-metal dielectric layer connecting with the metal plugs, and a passivation layer disposed over the top metal layer with a plurality of openings to expose the top metal layer portions as bonding pads, wherein at least one bonding pad is mark-shaped to indicate the orientation of the bonding pads on the semiconductor substrate. [0013] According to the present invention, the shape of the mark-shaped bonding pad on the above bonding pad structure can be, for example, a shape, a shape, a cross shape or a shape. [0014] According to the present invention, the top metal and the bottom metal layers on the bonding pad structure can be, for example, an alloy of aluminum and copper or an alloy of aluminum, copper and silica. The inter-metal dielectric layer can be silicon oxide and the passivation layer can be silicon oxide or borophosphosilicate glass and silicon nitride. [0015] The mark-shaped bonding pads on a wafer can be used as alignment markers for wafer dicing. The dicing machine can cut dies from a wafer by aligning with the mark-shaped bonding pads on the wafer surface. When the dies are cut from the wafer for further wire bonding, the orientation of circuits in the dies can be easily identified according to the mark-shaped bonding pads on the die surface. [0016] A probe pad with a mark-shape is further provided according to the present invention. The probe pad is disposed on a semiconductor circuit for electric characteristic measurement which has a mark-shape to indicate the relative location of the probe pad on the semiconductor circuit. [0017] According to the present invention, the shape of the mark-shaped probe pad on the semiconductor circuit can be, for example, a shape, a shape, a cross shape or a shape. The probe pad can be, for example, an alloy of aluminum and copper or an alloy of aluminum, copper and silica. [0018] An inspector can easily identify the orientation of the target circuit under a microscopic with the mark-shaped probe pads according to the present invention. BRIEF DESCRIPTION OF THE DRAWINGS [0019] The present invention will become more fully understood from the detailed description given herein below and the accompanying drawings, given by way of illustration only and thus not intended to be limitative of the present invention. In the drawings, [0020] FIG. 1 schematically shows a conventional die array on a wafer; Continue reading about Pad structure for bonding pad and probe pad and manufacturing method thereof... Full patent description for Pad structure for bonding pad and probe pad and manufacturing method thereof Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Pad structure for bonding pad and probe pad and manufacturing method thereof patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. 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