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10/26/06 - USPTO Class 324 |  102 views | #20060238187 | Prev - Next | About this Page  324 rss/xml feed  monitor keywords

Packaging of electronic chips with air-bridge structures

USPTO Application #: 20060238187
Title: Packaging of electronic chips with air-bridge structures
Abstract: A circuit assembly for fabricating an air bridge structure and a method of fabricating an integrated circuit package capable of supporting a circuit assembly including an air bridge structure. A circuit assembly comprises an electronic chip and a conductive structure embedded in a plurality of materials having a plurality of vaporization temperatures. The plurality of materials is formed on the electronic chip and the conductive structure is coupled to the electronic chip. To fabricate the circuit assembly, a support structure, including interstices, is formed on an electronic chip. The interstices of the support structure are filled with a material having a vaporization temperature that is less than the vaporization temperature of the support structure. Conductive structures are embedded in the support structure and the material, and a connective structure is mounted on the support structure. Finally, the material is removed from the interstices by heating the circuit assembly. (end of abstract)



Agent: Schwegman, Lundberg, Woessner & Kluth, P.A. - Minneapolis, MN, US
Inventor: Paul A. Farrar
USPTO Applicaton #: 20060238187 - Class: 324100000 (USPTO)

Packaging of electronic chips with air-bridge structures description/claims


The Patent Description & Claims data below is from USPTO Patent Application 20060238187, Packaging of electronic chips with air-bridge structures.

Brief Patent Description - Full Patent Description - Patent Application Claims
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RELATED APPLICATIONS

[0001] This application is a Divisional of U.S. application Ser. No. 09/382,929, filed Aug. 25, 1999, which is incorporated herein by reference.

FIELD OF THE INVENTION

[0002] This invention relates to the packaging of electronic chips, and more particularly to the packaging of electronic chips having air-bridge structures.

BACKGROUND OF THE INVENTION

[0003] As the density of devices, such as resistors, capacitors, and transistors, in an integrated circuit is increased, the distance between the signal carrying conductors is decreased, and the capacitive coupling between the conductors is increased. Several problems result from the increased capacitive coupling. First, the increased capacitive coupling reduces the rate at which information can be transferred along each of the signal carrying conductors. Second, the increased capacitive coupling between the signal carrying conductors reduces the noise margin on the conductors. In the worst case, a signal on one signal carrying conductor is capacitively coupled to an adjacent signal carrying conductor, and the information on the adjacent conductor is destroyed. Since it is desirable to avoid destroying information, it is also desirable to reduce the capacitive coupling between the signal carrying conductors of an integrated circuit.

[0004] In an integrated circuit, decreasing the dielectric constant of an insulator that separates two adjacent signal carrying conductors reduces the capacitive coupling between the two adjacent signal carrying conductors. Silicon dioxide is the most commonly used insulator in the fabrication of integrated circuits and has a relatively high dielectric constant of about four. Carbon dioxide has a smaller dielectric constant than silicon dioxide, so replacing silicon dioxide with carbon dioxide reduces the capacitive coupling between the two adjacent conductors. Unfortunately, the thermal conductivity of carbon dioxide is much less than the thermal conductivity of silicon dioxide. This lower thermal conductivity causes a reduction in the rate at which heat is conducted away from an integrated circuit chip that employs a carbon dioxide insulator, which can result in the catastrophic failure of the integrated circuit.

[0005] Air has a dielectric constant of one, which is less than the dielectric constant of carbon dioxide and much less than the dielectric constant of silicon dioxide. Replacing silicon dioxide with air in an integrated circuit reduces the capacitive coupling between signal carrying conductors. Air bridge structures, which are structures consisting primarily of signal carrying conductors surrounded by air in an integrated circuit, are fabricated to reduce the dielectric constant in the conductive structures of an integrated circuit. Unfortunately, since, in an air bridge structure, the signal carrying conductors are no longer embedded in a layer of silicon dioxide, the structural integrity of the integrated circuit is decreased. This problem is especially significant when an integrated circuit fabricated using air bridge structures is packaged as a flip chip,

[0006] For these an other reasons there is a need for the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS

[0007] FIG. 1 is a cutaway perspective view of some embodiments of an integrated circuit assembly employing a ribbed support structure of the present invention.

[0008] FIG. 2A is a cross-sectional view of the integrated circuit assembly of FIG. 1 along the section line 2.

[0009] FIG. 2B is a cross-sectional view of the integrated circuit assembly of FIG. 1 along the section line 3.

[0010] FIG. 3 is a perspective view of some embodiments of an integrated circuit assembly of the present invention employing a post support structure.

[0011] FIG. 4 is a perspective view of some embodiments of an integrated circuit assembly mounted on a substrate.

[0012] FIG. 5A is a simplified schematic of an air-bridge structure supported by conductive posts.

[0013] FIG. 5B is a simplified schematic of an air-bridge structure supported by insulating posts.

[0014] FIG. 6 is a block diagram of a computer system suitable for use in connection with the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0015] The above mentioned problems with air bridge structures, closely spaced conductors, silicon dioxide insulators and other problems are addressed by the various embodiments of the present invention and will be understood by reading and studying the following specification.

[0016] In the following detailed description of the preferred embodiments, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration specific preferred embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention, and it is to be understood that other embodiments may be utilized and that logical, mechanical and electrical changes may be made without departing from the spirit and scope of the present inventions. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims.

[0017] FIG. 1 is a cutaway perspective view of some embodiments of integrated circuit assembly 100 of the present invention. Integrated circuit assembly 100, in one embodiment, includes electronic chip 103, and material layer 106, comprising ribbed support structure 109, fill material 112, conductive structure 115, and interstices 116. In an alternate embodiment, integrated circuit assembly 100 also includes controlled collapse chip connection (C4) structure 118 comprising insulation layer 121, vaporization plug 124, and conductive elements 127 and 130.

[0018] Integrated circuit assembly 100 is not limited to use in connection with a particular type of electronic chip 103. Memory chips, such as a dynamic random access memory (DRAM) chips, static random access memory (SRAM) chips, read-only-memory (ROM) chips, and random access memory (RAM) chips, microprocessor chips, logic chips, digital signal processing chips, analog signal processing chips, and application specific integrated circuit (ASIC) chips can all be used in connection with integrated circuit assembly 100.

[0019] Material layer 106 is fabricated on the surface of electronic chip 103, and has a plurality of vaporization temperatures. In one embodiment, material layer 106 is fabricated from a plurality of materials in which each of the plurality of materials has a different vaporization temperature.

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