| Package modification for channel-routed circuit boards -> Monitor Keywords |
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Package modification for channel-routed circuit boardsRelated Patent Categories: Electricity: Conductors And Insulators, Conduits, Cables Or Conductors, Preformed Panel Circuit Arrangement (e.g., Printed Circuit), With Particular Conductive Connection (e.g., Crossover), FeedthroughPackage modification for channel-routed circuit boards description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20050257958, Package modification for channel-routed circuit boards. Brief Patent Description - Full Patent Description - Patent Application Claims
CROSS-REFERENCE TO RELATED APPLICATIONS [0001] This patent application is a continuation of U.S. patent application Ser. No. 10/437,006, filed May 14, 2003, which is hereby incorporated by reference herein in its entirety. FIELD OF THE INVENTION [0002] The present invention relates generally to multilayer circuit boards and, more particularly, to a technique for implementing through hole-based circuit components in multilayer circuit boards having channel routing. BACKGROUND OF THE INVENTION [0003] The limitations inherent to single signal layer printed circuit boards (PCBs) have led to the development of multilayer PCBs. Such multilayer PCBs may be either single or double-sided and may have multiple signal layers on the surface of and buried within the multilayer PCBs. [0004] While the number of layers that may be provided by a multilayer PCB is theoretically unlimited, problems occur when the number of layers in a multilayer PCB exceeds a reasonable number, particularly when trying to route high-speed electrical signals between electronic components. For example, when making electrical connections between different layers in multilayer PCBs, electrically conductive vias generally are used. While these electrically conductive vias allow direct vertical electrical connections to be made between different layers within a multilayer PCB, there are intrinsic parasitics associated with these electrically conductive vias that can adversely affect the performance of signals propagating therethrough. That is, these electrically conductive vias have intrinsic parasitic resistance, capacitance, and inductance which can adversely affect signals propagating along each electrically conductive via. In addition, these intrinsic parasitics can also have an adverse effect on the manufacturability of a PCB and thus the cost thereof. Because of their adverse affect on signal performance, these intrinsic parasitics can also limit the bandwidth of signals propagating along each electrically conductive via. These adverse affects only increase as the number of layers in a multilayer PCB increase. [0005] Due to the adverse effects on signal integrity as the layer count of a PCB increase, techniques have been developed to provide for "channel routing" within a PCB to reduce the number of layers necessary to provide the requisite electrical connections. An exemplary channel routing technique is described in U.S. Pat. No. 6,388,890 issued on May 14, 2002 to Kwong et al., the entirety of which is hereby incorporated by reference herein. Kwong et al. disclose a technique for manufacturing and using a PCB wherein certain vias extend only through a subset of the layers of the PCB to create channels in the portions of the PCB where vias are absent. These channels then may be used to route a larger number of signal, power, ground and/or test traces between vias thereby reducing the number of layers necessary to provide a certain number of electrical connections. [0006] While reducing the requisite number of signal layers, conventional channel routing techniques typically are limited to surface mount devices (SMDs), e.g., ball grid array (BGA) packages. Through hole-based devices (THDs), such as pin grid array (PGA) packages, generally have pins of a pre-determined length that may be incompatible with the reduced-depth vias used in PCBs having channel routing. As a result, THDs and other devices having pins of a uniform length often cannot be utilized in channel-routed PCBs and therefore are utilized with other types of PCBs that require a greater number of signal layers. This increased number of requisite signal layers may then create or magnify the adverse signal effects caused by an increased number of layers, as described above. [0007] In view of the foregoing, it would be desirable to provide a technique for implementing a THD and other pin-based. packages in a multilayer channel routed PCB. SUMMARY OF THE INVENTION [0008] A method for implementing a circuit component on a surface of a multilayer circuit board is provided in accordance with one embodiment of the present invention. The circuit component includes a plurality of pins and the circuit board includes a plurality of electrically conductive vias penetrating at least one layer of the circuit board and being arranged so as to form at least one channel for routing one or more traces at one or more signal layers of the circuit board. The method comprises the step of forming at least one pin of the plurality of pins of the circuit component to have a length compatible with a depth of a corresponding via of the circuit board. [0009] In accordance with another embodiment of the present invention, there is provided a circuit component for use with a multilayer circuit board having a plurality of electrically conductive vias penetrating at least one layer of the circuit board and being arranged so as to form at least one channel for routing one or more traces at one or more signal layers of the circuit board. The circuit component comprises a plurality of pins corresponding to the plurality of vias of the multilayer circuit board, each pin having a length compatible with a depth of the corresponding via. [0010] In accordance with yet another embodiment of the present invention, a circuit device is provided. The circuit device comprises a multilayer circuit board having a plurality of electrically conductive vias penetrating at least one layer of the circuit board and being arranged so as to form at least one channel for routing one or more traces at one or more signal layers of the circuit board. The circuit device further comprises a circuit component mounted to a surface of the circuit board and having a plurality of pins corresponding to the plurality of vias, each pin extending into and in electrical contact with the corresponding via of the circuit board, wherein each of the plurality of pins of the circuit component has a length compatible with a depth of the corresponding via. [0011] The present invention will now be described in more detail with reference to exemplary embodiments thereof as shown in the appended drawings. While the present invention is described below with reference to preferred embodiments, it should be understood that the present invention is not limited thereto. Those of ordinary skill in the art having access to the teachings herein will recognize additional implementations, modifications, and embodiments, as well as other fields of use, which are within the scope of the present invention as disclosed and claimed herein, and with respect to which the present invention could be of significant utility. BRIEF DESCRIPTION OF THE DRAWINGS [0012] In order to facilitate a fuller understanding of the present invention, reference is now made to the appended drawings. These drawings should not be construed as limiting the present invention, but are intended to be exemplary only. [0013] FIG. 1A is a flow diagram illustrating an exemplary method for creating a circuit device having a package modified to conform to a circuit board having channel routing in accordance with at least one embodiment of the present invention. [0014] FIG. 1B is a schematic diagram illustrating a plan and cross-section view of an exemplary circuit board having channel routing and a cross section of an exemplary package having pins modified to conform to the circuit board in accordance with at least one embodiment of the present invention. [0015] FIG. 1C is a schematic diagram illustrating a joining of the package and circuit board of FIG. 1B in accordance with at least one embodiment of the present invention. [0016] FIG. 2A is a flow diagram illustrating an exemplary method for creating a circuit device having a package manufactured to conform to a circuit board having channel routing in accordance with at least one embodiment of the present invention. [0017] FIG. 2B is a schematic diagram illustrating a plan and cross-section view of an exemplary circuit board having channel routing and a cross section of an exemplary package having pins manufactured to conform with the circuit board in accordance with at least one embodiment of the present invention. [0018] FIG. 2C is a schematic diagram illustrating a joining of the package and circuit board of FIG. 2B in accordance with at least one embodiment of the present invention. [0019] FIG. 3A is a schematic diagram illustrating a cross section view of an exemplary fixture used to form pins having certain lengths in accordance with at least one embodiment of the present invention. Continue reading about Package modification for channel-routed circuit boards... Full patent description for Package modification for channel-routed circuit boards Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Package modification for channel-routed circuit boards patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. Start now! - Receive info on patent apps like Package modification for channel-routed circuit boards or other areas of interest. ### Previous Patent Application: Structurally integrated circuit and associated method Next Patent Application: Microtunneling systems and methods of use Industry Class: Electricity: conductors and insulators ### FreshPatents.com Support Thank you for viewing the Package modification for channel-routed circuit boards patent info. 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