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Package-integrated thin film led

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Package-integrated thin film led


LED epitaxial layers (n-type, p-type, and active layers) are grown on a substrate. For each die, the n and p layers are electrically bonded to a package substrate that extends beyond the boundaries of the LED die such that the LED layers are between the package substrate and the growth substrate. The package substrate provides electrical contacts and conductors leading to solderable package connections. The growth substrate is then removed. Because the delicate LED layers were bonded to the package substrate while attached to the growth substrate, no intermediate support substrate for the LED layers is needed. The relatively thick LED epitaxial layer that was adjacent the removed growth substrate is then thinned and its top surface processed to incorporate light extraction features. There is very little absorption of light by the thinned epitaxial layer, there is high thermal conductivity to the package because the LED layers are directly bonded to the package substrate without any support substrate therebetween, and there is little electrical resistance between the package and the LED layers so efficiency (light output vs. power input) is high. The light extraction features of the LED layer further improves efficiency.
Related Terms: Solder

USPTO Applicaton #: #20130313562 - Class: 257 76 (USPTO) - 11/28/13 - Class 257 
Active Solid-state Devices (e.g., Transistors, Solid-state Diodes) > Specified Wide Band Gap (1.5ev) Semiconductor Material Other Than Gaasp Or Gaalas

Inventors: John Edward Epler, Paul S. Martin, Michael R. Krames

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The Patent Description & Claims data below is from USPTO Patent Application 20130313562, Package-integrated thin film led.

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CROSS-REFERENCE TO RELATED APPLICATIONS

This is a continuation of U.S. application Ser. No. 12/969,709, filed Dec. 16, 2010 by John Epler et al., titled “Package-Integrated Thin Film LED,” now U.S. Pat. No. 8,455,913, which is a division of U.S. application Ser. No. 12/368,213, now U.S. Pat. No. 7,875,533, which is a continuation of U.S. application Ser. No. 11/421,350, now U.S. Pat. No. 7,488,621, which is a division of U.S. Ser. No. 10/977,294, now U.S. Pat. No. 7,256,483. Each of U.S. Pat. No. 8,455,913, U.S. Pat. No. 7,875,533, U.S. Pat. No. 7,488,621, and U.S. Pat. No. 7,256,483 is incorporated herein by reference.

FIELD OF THE INVENTION

This invention relates to light emitting diodes (LEDs) and, in particular, to a technique for mounting LED dies for packaging so the packaged LEDs have improved optical, electrical, and thermal characteristics.

BACKGROUND

LEDs are formed by growing epitaxial layers, including p-type and n-type layers, on a growth substrate. A light-emitting active layer is sandwiched between the n and p layers. Green, blue, and ultraviolet LEDs are typically gallium-nitride based, where the growth substrate is typically either sapphire (an insulator), SiC (a semiconductor), silicon, SiC-on-insulator (SiCOI), or other engineered substrate. Infrared, red, and amber LEDs are typically some combination of AlInGaPAs and grown on a GaAs or InP substrate. The growth substrate has a lattice structure similar to the lattice structure of the LED material.

It is sometimes desirable to remove the growth substrate to, for example, improve the optical properties of the LED or to gain electrical access to the LED layers. In the case of a sapphire substrate, removal may be by means of laser melting a GaN/sapphire interface. In the case of Si or GaAs substrates, more conventional selective wet etches may be utilized to remove the substrate.

Since the LED epitaxial layers are extremely thin (e.g., less than 10 microns) and delicate, before removing the growth substrate, the LED wafer must first be attached to a support substrate so that the LED layers are sandwiched between the growth substrate and the support substrate. The support substrate has the desired optical, electrical, and thermal characteristics for a particular application of the LED. The growth substrate is then removed by known processes. The resulting wafer with the support substrate and LED layers is then diced, and the LED dice are then mounted in packages.

A package typically includes a thermally conductive plate with electrical conductors running from the die attach region to the package terminals. The p and n type layers of the LED are electrically connected to the package conductors. In the case of a vertical injection device, the support substrate is metal bonded to the package, providing a current path to the n or p-type LED layers adjacent to the support substrate, and the opposite conductivity type layers are connected via a wire (e.g., a wire ribbon) to a package contact pad. In the case of a flip-chip LED (n and p-type layers exposed on the same side), both n and p-connections are formed by die attaching to multiple contact pads patterned to mate to the n and p-contact metallizations on the die. No wires are required.

Some drawbacks with the above-described devices are described below.

The support substrate between the LED layers and the package provides some electrical and thermal resistance, which is undesirable. The support substrate itself adds expense and height. The process of attaching the support substrate to the LED wafer is costly, and yield is lowered.

Accordingly, what is needed is a technique to avoid the above-described drawbacks.

SUMMARY

LED epitaxial layers (n-type, p-type, and active layers) are grown on a substrate. In one example, the LED is a GaN-based LED, and a relatively thick (approx. 1-2 micron) GaN layer (typically n-type) is grown on the substrate to provide a low-stress transition between the substrate crystal lattice structure and the GaN crystal lattice structure.

The top LED layer (typically p-type) on the wafer is metallized, and the wafer is diced into separate LED elements. For each die, the metallized layer is metal bonded to a package substrate that extends beyond the boundaries of the LED die such that the LED layers are between the package substrate and the growth substrate. The package substrate provides electrical contacts and traces leading to solderable package connections.

For each individual chip, the growth substrate is then removed.

The GaN transition layer is then thinned and its top surface textured, patterned, shaped, or roughened to improve light extraction. The thinning reveals (exposes) the n-GaN contact layer, removes the less transparent nucleation layer, and removes crystal damage caused during the growth substrate removal.

If the LED is a vertical injection device, an electrical contact to the thinned GaN layer (usually n-type) is required. A suitable metal contact is formed on the GaN layer, and a wire ribbon or a metal bridge is provided between a contact pad on the package substrate and the contact on the GaN layer. If the LED is a flip chip design, n and p contacts are formed on the side of the LED facing the package substrate and are bonded to contact pads on the package substrate without a wire.

The LED layers are extremely thin (less than 50 microns and typically less than 3 microns) so there is very little absorption of light by the thinned GaN layer; there is high thermal conductivity to the package because the LED layers are directly bonded to the package substrate without any support substrate therebetween; and there is little electrical resistance between the package and the LED layers so efficiency (light output vs. power) is high. The light extraction features (e.g., roughening) of the GaN layer further improves efficiency.

A process is also described where the LED layers are transferred to the package substrate without first being diced. The entire growth substrate is then removed intact so that it may be reused.

The process may be performed on LEDs that are not GaN-based. Other embodiments are described.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross-sectional view of an LED die, using a sapphire growth substrate, mounted on a package substrate.



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Active solid-state devices (e.g., transistors, solid-state diodes)
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stats Patent Info
Application #
US 20130313562 A1
Publish Date
11/28/2013
Document #
13908003
File Date
06/03/2013
USPTO Class
257 76
Other USPTO Classes
438 28, 438 22
International Class
/
Drawings
7


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