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Output buffer with time varying source impedance for driving capacitively-terminated transmission linesOutput buffer with time varying source impedance for driving capacitively-terminated transmission lines description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20050280435, Output buffer with time varying source impedance for driving capacitively-terminated transmission lines. Brief Patent Description - Full Patent Description - Patent Application Claims
BACKGROUND OF THE INVENTION [0001] 1. Field of the Invention [0002] This invention relates to the field of transmission line drivers, and particularly to circuits and methods for driving capacitively-terminated transmission lines. [0003] 2. Description of the Related Art [0004] Transmission lines are used to convey high frequency digital data signals between a source circuit and a destination circuit. The destination circuit can be considered a load, which typically includes a capacitive component. Transmission lines having a capacitive load at their receiving end are referred to herein as capacitively-terminated transmission lines. [0005] A transmission line has a characteristic impedance Z.sub.0, as does the load being driven. Ideally, the impedances of the load and the transmission line are equal; when so arranged, a data signal transition that occurs at the source end of the transmission line is fully absorbed by the load, with none of the energy reflected back towards the source by the load. However, it is often impossible to make the transmission line and load impedances equal. For example, in digital circuits the load is often a transistor gate whose impedance is almost purely capacitive. A capacitive load causes all of the incident energy to be reflected back toward the source in a negative voltage wave. In some instances, a load resistor is added to the capacitive load in an attempt to properly terminate the transmission line. However, the capacitance at the end of the transmission line shunts out the load resistance at higher frequencies, resulting in an impedance mismatch; consequently, with a capacitive load impedance the data signal transition is at least partially reflected back towards the source. When this negative wave propagates to the source end of the transmission line, it may again be reflected back towards the load, thereby distorting the data signal being conveyed. The output impedance of the source circuit is typically much lower than Z.sub.0, which allows for a large pulse amplitude to be delivered to the transmission line. This creates a fast transition slew rate at the capacitively-terminated end of the transmission line. However, a low output impedance tends to maximize the magnitude of the signal reflected by the source back towards the load, and thus the data signal distortion. The above principle is applicable to any complicated capacitively-terminated transmission line. [0006] The problem noted above tends to become more acute as the frequency of the transitions increases; i.e., data signal distortion is less for a data bit pattern of 111000 than it is for a pattern of 101010. "Waveshaping" the data bit signal is sometimes used to mitigate this problem. One such approach requires looking ahead at a predetermined number of upcoming data bits, and increasing the amplitude of the transmitted signal when the transition frequency increases. However, this approach requires complex look-ahead and output voltage adjustment circuitry, which does nothing to reduce the magnitude of the reflected waves, or to address their causes. SUMMARY OF THE INVENTION [0007] An output buffer is presented which overcomes the problems noted above, providing high-speed transitions while mitigating the effects of waves reflected by a capacitive load at the terminal end of a transmission line. [0008] The present output buffer is intended for driving a capacitively-terminated transmission line which conveys data bits via the transmission line during respective unit intervals. The buffer's output waveform comprises a first portion, during which it transitions from a first voltage V1 to a second voltage V2 between a time t1 and a time t2; a second portion during which it remains fixed at V2 until a time t3; a third portion during which it transitions to a voltage V3 between V1 and V2 between time t3 and a time t4; and a fourth portion during which it remains fixed at V3 until a time t5. The output buffer waveform is created within a unit interval whenever successive data bits transition between logic states--i.e., when a "1" is followed by a "0", or a "0" is followed by a "1". [0009] The invention requires that the output buffer generate the first and second portions of the waveform with circuitry having an output impedance Z.sub.1 much lower than the characteristic impedance Z.sub.0 of the transmission line such that voltage V3 is maximized. The invention further requires that the fourth output buffer waveform portion be generated with output buffer circuitry which has a non-zero output impedance Z.sub.2, greater than Z.sub.1 and preferably equal to Z.sub.0, to absorb transitions reflected back to the source circuitry by the capacitive termination. [0010] The low-Z source impedance during the first and second waveform portions increases the initial voltage delivered into the transmission line (when compared with a standard Z.sub.0 source impedance), thereby causing the capacitive load to receive a larger incident pulse such that it is quickly charged, which increases the slew rate at the capacitive load. To mitigate the effect of the wave reflected by the load, the duration of the first and second portions is preferably made less than the twice the data bit's transit time on the transmission line, such that the output impedance Z.sub.2 (preferably=Z.sub.0) associated with the fourth portion is in place to absorb and/or dissipate the reflected wave and thereby reduce the data signal distortion that might otherwise occur. Overshoot and undershoot problems are also reduced, as the absorption of the reflected wave by Z.sub.2 and the lower voltage fourth waveform portion tend to reduce the magnitude of any ringing on the transmission line. [0011] Further features and advantages of the invention will be apparent to those skilled in the art from the following detailed description, taken together with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS [0012] FIG. 1a is a diagram of an output buffer and capacitively-terminated transmission line per the present invention. [0013] FIG. 1b is a timing diagram for an output buffer waveform in accordance with the present invention. [0014] FIG. 1c is a timing diagram showing the transmission of several successive data bits in accordance with the present invention. [0015] FIG. 2a is one possible embodiment of an output buffer per the present invention. [0016] FIG. 2b is a timing diagram illustrating the operation of the output buffer shown in FIG. 2a. [0017] FIG. 2c is another possible embodiment of an output buffer per the present invention. [0018] FIG. 3a is an n branch embodiment of the output buffer shown in FIG. 2a. [0019] FIG. 3b is an n branch embodiment of the output buffer shown in FIG. 2c. [0020] FIG. 3c is a timing diagram illustrating the operation of the output buffers shown in FIGS. 3a and 3b. [0021] FIG. 4a is a timing diagram comparing the results achievable by the present output buffer with a prior art buffer having a low output impedance. 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