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Operation-processing device, method for constructing the same, and operation-processing system and methodRelated Patent Categories: Data Processing: Database And File Management Or Data Structures, Database Schema Or Data Structure, Application Of Database Or Data Structure (e.g., Distributed, Multimedia, Image)Operation-processing device, method for constructing the same, and operation-processing system and method description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20080046470, Operation-processing device, method for constructing the same, and operation-processing system and method. Brief Patent Description - Full Patent Description - Patent Application Claims
TECHNICAL FIELD [0001] The present invention relates to an operation-processing device, a method for constructing the same, and an operation-processing system and method that are well applicable to a central processing unit (CPU) and a microprocessor unit (MPU), which perform various types of data processing based on a system program, a programmable logic-operation device (PLD), a programmable one-chip microcomputer that can be incorporated in such a built-in electronic apparatus, and the like. [0002] More specifically, it provides a register array for executing an operation instruction and an instruction execution controlling portion for controlling an operation portion to select one of the registers based on the operation instruction and perform register-to-register addressing processing that selects, based on a value held by this selected register, another register, thereby permitting the register array to operates like a memory that can read and write data at random and reducing an occupied area of a substrate as compared to the case of arranging a CPU, an RAM, a ROM, etc. on the substrate individually. [0003] According to the present invention, there is provided an operation-processing device for performing an arbitrary operation by specifying plural registers, to decode a type of the register by obtaining a compressed program created by a program creation system and restore the number of bits of an instruction which specifies this register based on the register type in order to restore a program having an instruction structure with a predetermined instruction length, thereby reducing a capacity of a memory such as a ROM to store data of the program and reducing an occupation ratio of memory cells which function as a ROM in a case where a processor is constituted of a PLD comprised of the memory cells and logic operation element. BACKGROUND ART [0004] Recently, a microprocessor including a central processing unit (CPU) has been often used in various types of electronic apparatuses such as a portable terminal device, an e-card, and an information-processing device. In a case where this type of processor tries to access a storage device, a different access method is executed depending on whether the access destination is a register or an external memory. If the access destination is a register, for example, in a periphery of an arithmetic/logic unit (ALU), a copy register, a temporary register, etc. are arranged, so that to perform arithmetic processing, data is copied to the copy register or operated data is temporarily stored in the temporary register. This is because an ALU is suited for performing of register-to-register operation processing. If the access destination is an external memory, for example, in a case where information is written to an external memory address indicated by this external memory, the CPU outputs to this external memory a write address to specify the storage address and a write signal. To read information from an external memory address indicated by the register number, the CPU outputs to the external memory a read address to specify the storage address and a read signal. [0005] In such a manner, to store information in an external memory address indicated by the register number or read it from the external memory address indicated by this register number, the CPU specifies a storage address (write address or read address) in this external memory. Such the processing is referred to as register-to-register addressing in many cases. This is because the external memory is typically mounted to a device different from the processor. [0006] Further, this type of processor is mounted, besides an instruction execution/operation portion, with a read only memory (hereinafter referred to as ROM) for storing an instruction execution program, many registers used in instruction execution/operation processing, etc. With a conventional type microprocessor, in the case of incorporating this processor into an arbitrary electronic apparatus, an instruction and a behavior to be executed by the instruction correspond to each other in a one-to-one relationship. That is, the number of bits of an instruction used to specify a register, irrespective of whether it used frequently or not, is made constant to often use a program created by using an instruction thus having a fixed length. Therefore, instruction with a fixed length is stored in a ROM and used. [0007] On the other hand, with developments of semiconductor integrated-circuit technologies, a vast number of registers can be mounted in a processor (hereinafter referred to as "operation-processing device"). In this case, a correspondingly larger number of bits are required of an instruction which identifies a register. For example, in a case where 1024 registers are mounted, to identify one of the 1024 registers, the instruction needs to have 10 bits. However, with an actual program, not all of registers have the same access frequency, so that there are fluctuations in access frequency. The No. of a register accessed frequently is typically decided by a compiler. [0008] With the conventional operation-processing device, a processing rate is decreased for the following reasons: [0009] {circle around (1)} It takes a certain lapse of time to access an external memory. Accordingly, the side of a processor must create an interface that matches a storage device to be accessed because typically the storage device is rarely made especially so as to match a specific processor. Therefore, each time the storage device is accessed, access goes through the interface, so that access time is increased to decrease an operation-processing speed; [0010] {circle around (2)} It takes a certain lapse of time to transfer data from an external memory to an ALU or vice versa. This is because an ALU typically accommodates register-to-register operation processing; in a case where there is data to be operated in the external memory, the data is once copied from the external memory to a copy register and then transferred from the copy register to the ALU so that it may undergo operation processing (register-to-memory addressing). It thus contributes to a decrease in operation-processing speed; [0011] {circle around (3)} To integrate functions of a CPU, an RAM, a ROM, etc. into one chip so as to constitute one-chip microcomputer etc., a method for arranging the CPU and, in its periphery, the RAM, the ROM, etc. on the same semiconductor chip may be considered. This method relies on the register-to-memory addressing and so cannot be expected to improve the operation-processing speed; [0012] {circle around (4)} Further, with the conventional operation-processing device, the following problems are involves in mounting of a ROM in which an instruction execution program is stored: [0013] Looking at whole codes of this instruction execution program, there is a few case where, from, for example, ten bits of an instruction for specifying a register, the entire ten bits are used evenly. Therefore, there exist many useless bits in a memory (for example, ROM or flash memory) for storing the instruction execution program. Accordingly, a method of representing every register by using the same number of instruction bits prevents the ROM from being used efficiently; [0014] {circle around (5)} Furthermore, to construct a microprocessor etc. with a programmable logic device (PLD) comprised of memory cells and logic operation elements, a method may be considered for arranging an instruction execution/operation portion and, in its periphery, a register array, a ROM, etc. on the same semiconductor chip. In this case, an increase in size of the instruction execution program owing to a demand for multi-functioning of the processor necessitates an increase in memory capacity of the ROM for storing this program. Therefore, the construct the ROM occupies the memory cells, so that it is difficult to allocate many of the memory cells to the register. DISCLOSURE OF THE INVENTION [0015] A first operation-processing device related to the present invention is a device for performing operation processing based on an arbitrary operation program. This operation-processing device comprises a register array having plural registers each for holding an arbitrary value based on a write address and a write control signal and outputting this value based on a read address, an operation portion for performing operation on a value read from this register array, an instruction-decoding portion for decoding an operation instruction from an operation program for operating this operation portion, and an instruction-execution-controlling-portion for controlling the register array and the operation portion in order to execute an operation instruction decoded by this instruction-decoding portion. This instruction-execution-controlling portion selects one of the registers based on the operation instruction and, based on a value held by the selected register, performs register-to-register addressing processing for selecting another register. [0016] According to this first operation-processing device, to perform operation processing based on an arbitrary operation program, the instruction-decoding portion decodes an operation instruction from the operation program for operating the operation portion. To execute the operation instruction decoded by the instruction-decoding portion, the instruction-execution-controlling portion controls the register array and the operation portion. On this assumption, the instruction-execution-controlling portion selects one of the registers based on the operation instruction and based on a value held by this selected register, performs register-to-register addressing processing for selecting another register. Each of the registers that constitute the register array holds an arbitrary value based on the write control signal and a write address specified by the register-to-register addressing processing and outputs this value based on a read address. The operation portion performs operations on the value read from the register array. [0017] The register array can thus be used as if it is a data random access memory (RAM), so that it depends on register-to-memory addressing processing that specifies an external memory storage address less than a conventional central processing unit (CPU) does. Functions of an RAM and a ROM can be incorporated into the conventional CPU, so that it is Z possible to execute high-speed operation processing and reduce an area of a substrate occupied by the CPU, the RAM, the ROM, etc. as compared to a case where they are arranged individually on the substrate. An applied device to which this operation-processing device is applied can be compacted. Moreover, on the same semiconductor chip, the register array and the read only memory can be constituted of memory cells and the operation portion, the instruction-decoding portion, and the instruction-execution-controlling portion can be constituted of arithmetic/logic operation elements, thereby constituting this operation-processing device of a programmable logic device. [0018] A constructing method of each operation-processing device related to the present invention is a method for constructing a device for performing operation processing based on an arbitrary operation program. This constructing method comprises the steps of forming plural memory cells and arithmetic/logic operation elements on the same semiconductor chip beforehand, combining the memory cells to define a register array and a read only memory and combining the arithmetic/logic operation elements to define an operation portion, an instruction-decoding portion, and an instruction-execution-controlling portion, and connecting the register array, the read only memory, the operation portion, the instruction-decoding portion, and the instruction-execution-controlling portion to each other based on preset wiring information and writing an arbitrary operation program to the read only memory. [0019] According to the constructing method for constructing the operation-processing device related to the present invention, for example, upon power application, wiring information is read from a nonvolatile storage portion and, based on the wiring information, the register array, the read only memory, the operation portion, the instruction-decoding portion, and the instruction-execution control portion are connected to each other. Therefore, it is possible to construct such a programmable operation-processing device, upon power application, that the instruction-execution-controlling portion selects one of the registers based on an operation instruction and, based on a value held by this register, it performs register-to-register addressing for selecting another register. Moreover, it is possible to construct an operation-processing device that has incorporated functions of an RAM and a ROM into a conventional CPU, thereby executing high-speed operation processing and reducing an area of a substrate occupied by the CPU, the RAM, the ROM, etc. as compared to a case where they are arranged on the substrate individually. An applied device to which this operation-processing device is applied can be compacted. [0020] A first operation-processing method related to the present invention is a method for performing arbitrary operation processing based on an operation program. This operation-processing method comprises the steps of beforehand preparing plural registers each for holding an arbitrary value based on a write address and a write control signal and outputting this value based on a read address, then decoding an operation instruction from the operation program, selecting one of the registers based on the operation instruction, performing register-to-register addressing processing for selecting, based on a value held by this selected register, another register, and performing operation on a value held by the selected another register and a value of the register selected by the register-to-register addressing processing. [0021] According to this first operation-processing method, in a case where arbitrary operation processing is performed on the basis of the operation program, the plural registers can be handled as if they are a data random access memory, so that it depends on register-to-memory addressing processing less than a conventional operation-processing method that has combined the central processing unit and an external memory does. It is thus possible to perform high-speed operation processing as compared with the conventional one. [0022] A second operation-processing device related to the present invention is a device for performing operation processing based on an operation program for performing register-to-register addressing processing, comprising plural registers, a storage portion for storing a compressed program having a different instruction length in which the number of bits of an instruction for specifying the register is reduced beforehand based on a frequency at which the registers are used and a type of the register is written in an instruction structure of the program, an instruction-decoding portion for reading the compressed program from the storage portion to decode a register type and, based on this register type, restore the number of bits of the instruction for specifying the register; and an instruction execution/operation portion for performing an arbitrary operation by specifying the register based on the instruction having a predetermined length restored by the instruction-decoding portion. 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