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08/10/06 - USPTO Class 365 | 113 views | #20060176738 | Prev - Next | About this Page

Novel monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout

Title: Novel monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout

Brief Patent Description - Full Patent Description - Patent Claims

The Patent Description & Claims data below is from USPTO Patent Application 20060176738, Novel monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout.

1. A method for forming a nonvolatile memory cell comprising steps of forming a source region and drain region spatially separated within a surface of a substrate; forming a tunneling insulator upon said surface of said substrate in a channel region between the source region and the drain region; forming a floating gate placed over the channel region of said memory cell; aligning said floating gate with an edge of said source region and an edge of said drain region; setting a width of said floating gate to be a width of said edge of said source and said edge of said drain; and forming an insulating layer upon said floating gate; and forming a control gate upon said insulating layer above said floating gate.

2. The method for forming the nonvolatile memory cell of claim 1 further comprising the step of defining an area of said floating gate such that said nonvolatile memory cell has a relatively small coupling ratio of capacitance formed by a control gate placed over said floating gate to a total capacitance of said floating gate and said control gate.

3. The method for forming the nonvolatile memory cell of claim 2 wherein said coupling ratio is less than 50%.

4. The method for forming a nonvolatile memory cell of claim 1 further comprising the steps of: connecting said control gate to a word line; placing said drain region in communication with a bit line; and connecting said source region to a source line.

5. The method for forming the nonvolatile memory cell of claim 2 wherein said the nonvolatile memory cell is programmed to place a charge upon said floating gate by the steps of: applying a moderately high positive voltage to said control gate through said word line; applying an intermediate positive voltage to said drain region through said bit line; and applying a ground reference voltage to said source region through said source line.

6. The method for forming the nonvolatile memory cell of claim 5 wherein said moderately high positive voltage is from approximately +10.0V to approximately +12.0V.

7. The method for forming the nonvolatile memory cell of claim 5 wherein said intermediate positive voltage is approximately 6.0V such that approximately 5.0V is applied to the drain region.

8. The method for forming the nonvolatile memory cell of claim 5 wherein applying said moderately high positive voltage, said intermediate positive voltage, and applying said ground reference voltage has a duration of from approximately 1 .mu.s to approximately 100 .mu.s.

9. The method for forming the nonvolatile memory cell of claim 4 wherein said memory cell is erased to remove electrical charge from said floating gate by the steps of: applying a very large negative voltage to said control gate through said word line.

10. The method for forming the nonvolatile memory cell of claim 9 wherein the very large negative voltage is from approximately -15V to approximately -22V.

11. The method for forming the nonvolatile memory cell of claim 9 wherein erasing said memory cell further comprises the step of: disconnecting the source line and said bit line to allow said source region and said drain region to float.

12. The method for forming the nonvolatile memory cell of claim 9 wherein erasing said memory cell further comprises the step of: applying a ground reference voltage to said source region through said source line and said drain region through said bit line.

13. The method for forming the nonvolatile memory cell of claim 9 wherein erasing said memory cell has a duration of from approximately 1 ms to approximately 1 s.

14. The method for forming the nonvolatile memory cell of claim 4 further comprising the step of forming a gating transistor by the steps of: forming a source; connecting said source to the drain region, forming a drain, connecting said drain to the bit line; forming a gate; connecting said gate to a select line to selectively apply a bit line voltage signal to the drain region.

15. The method for forming the nonvolatile memory cell of claim 14 wherein said nonvolatile memory cell is programmed to place a charge upon said floating gate by the steps of: applying a moderately high positive voltage to said control gate through said word line; applying an intermediate positive voltage to said drain region through said gating transistor from said bit line; applying a very large positive voltage to said gate of said gating transistor through said gate line; and applying a ground reference voltage to said source region through said source line.

16. The method for forming the nonvolatile memory cell of claim 15 wherein said moderately high positive voltage is from approximately +10.0V to approximately +12.0V.

17. The method for forming the nonvolatile memory cell of claim 15 wherein said intermediate positive voltage is approximately 6.0V such that approximately 5.0V is applied to the drain region.

18. The method for forming the nonvolatile memory cell of claim 15 wherein the very large positive voltage is from approximately +15V to approximately +22V.

19. The method for forming the nonvolatile memory cell of claim 15 wherein applying said very large positive voltage, said moderately high positive voltage, said intermediate positive voltage, and applying said ground reference voltage has a duration of from approximately 1 .mu.s to approximately 100 .mu.s.

20. The method for forming the nonvolatile memory cell of claim 14 wherein said memory cell is erased to remove electrical charge from said floating gate by the steps of: applying a very high positive voltage to said control gate through said word line; and applying a ground reference voltage to said select gate through said select line.

21. The method for forming the nonvolatile memory cell of claim 20 wherein erasing said memory cell further comprises the step of: disconnecting the source line and said bit line to allow said source region and said drain region to float.

22. The method for forming the nonvolatile memory cell of claim 20 wherein erasing said memory cell further comprises the step of: applying a ground reference voltage to said source region through said source line and said drain region through said gating transistor from said bit line.

23. The method for forming the nonvolatile memory cell of claim 20 wherein erasing said memory cell has a duration of from approximately 1 ms to approximately 1 s.

Brief Patent Description - Full Patent Description - Patent Claims

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Previous Patent Application:
Method for reading flash memory cell, nand-type flash memory apparatus, and nor-type flash memory apparatus
Next Patent Application:
Novel monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout
Industry Class:
Static information storage and retrieval

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