| Novel monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout -> Monitor Keywords |
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Novel monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layoutNovel monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20060176738, Novel monolithic, combo nonvolatile memory allowing byte, page and block write with no disturb and divided-well in the cell array using a unified cell structure and technology with a new scheme of decoder and layout. Brief Patent Description - Full Patent Description - Patent Application Claims
RELATED PATENT APPLICATIONS [0001] The present invention is a divisional application that claims priority under 35 U.S.C. .sctn.120 from U.S. patent application Ser. No. 10/351,180, filing date Jan. 4, 2003, now U.S. Pat. No. ______, issued ______; which is related to and claims benefit of priority of the filing date of U.S. Provisional Patent Application Ser. No. 60/394,202 filed on Jul. 5, 2002 and entitled "A Novel Monolithic Nonvolatile Memory Allowing Byte, Page and Block Write With No Disturb and Divided-Well in The Cell Array Using A Unified Cell Structure and Technology With A New Scheme of Decoder", which is herein incorporated by reference; and which is further related to and claims benefit of priority of the filing date of U.S. Provisional Patent Application Ser. No. 60/426,614 filed on Nov. 14, 2002, entitled "A Novel Monolithic, Combo Nonvolatile Memory Allowing Byte, Page And Block Write With No Disturb And Divided-Well In The Cell Array Using A Unified Cell Structure And Technology With A New Scheme Of Decoder And Layout ", which is herein incorporated by reference; and which is further related to and claims benefit of priority of the filing date of U.S. Provisional Patent Application Ser. No. 60/429,261 filed on Nov. 25, 2002, entitled "A Novel Monolithic, Combo Nonvolatile Memory Allowing Byte, Page And Block Write With No Disturb And Divided-Well In The Cell Array Using A Unified Cell Structure And Technology With A New Scheme Of Decoder And Layout", which is herein incorporated by reference. [0002] U.S. patent application Ser. No. 09/852,247 to F. C. Hsu et al filed on May 9, 2001 and assigned to the same assignee as the present invention. [0003] U.S. patent application Ser. No. 09/891,782 to F. C. Hsu et al filed on Jun. 27, 2001 and assigned to the same assignee as the present invention. BACKGROUND OF THE INVENTION [0004] 1. Field of the Invention [0005] This invention relates generally to a non-volatile integrated circuit memory. More particularly this invention relates to electrically erasable programmable read only memory (EEPROM) and flash electrically erasable programmable read only memory (flash memory). [0006] 2. Description of Related Art [0007] The structure and application of the floating gate nonvolatile memories is well known in the art. The floating gate nonvolatile memory has three classifications the Electrically Programmable Read Only Memory (EPROM), the Electrically Erasable Programmable Read Only Memory (EEPROM), and the flash Electrically Erasable Programmable Read Only Memory. The EPROM is programmed by electrically forcing charge to the floating gate. Ultra-violet light is employed to eliminate the electrical charges of the programming from the floating gate of the EPROM. The EEPROM and the flash memory are structurally similar at the individual cell, but have different organizations. The EEPROM and the flash memory maybe have the charge transferred to the floating gate for programming by either a channel hot injection of the charge or by Fowler-Nordheim Tunneling through a tunneling oxide. The erasure of the EEPROM and Flash memory is generally by a Fowler-Nordheim Tunneling through the tunneling oxide. [0008] A primary application of a nonvolatile memory is for permanent memory in a microprocessor or microcontroller system. Historically, the permanent program memory for the microprocessor was formed of classic mask programmable read only memory (ROM), and later as EPROM. Modifications to the program memory required physically changing the memory. As the need to update the program of the microprocessor became more important, byte-alterable EEPROM' were developed to provide in-system rewriteability of the memory. Further as the applications for microprocessors and microcontrollers are becoming more pervasive, the need for storage that is permanent and will not fail or disappear when power is removed is required. In most applications, the program is not modified often. However, the data is changed relatively frequently. The program memory can be classified as configuration, traceablity, boot program, or main program. The data includes information from any external input to the system, e.g., application, instrument, recorder, or sensor data that is required for historical purposes or to maintain continuity of operation after power down or power loss. Data memory is typically frequently altered over the lifetime of the application. [0009] The program memory is generally implemented in Flash memory. The Flash memory has memory size per erase that is usually large and is in the units of sector that ranges from 8 KB (64 K-bit) to 64 KB (6512 K-bit). Alternately, the data memory is implemented as EEPROM. The EEPROM used for a data memory must have segments that may be erased as small as single byte (8 bits), to a size of a single page (128-byte), and even to erasure of the whole chip. [0010] The ability of the EEPROM and the Flash memory to be reprogrammed requires the device be able to be altered in system, with minimal hardware or software difficulty. The number of times the device must be altered determines the endurance requirement of the device. Nonvolatility requires the device to retain data without power applied for the lifetime of the application. The lifetime of the application determines the data retention requirement of the device. Both of the reliability requirements of endurance and data retention have associated failure rates, which must be minimized. Since the flash memory is employed as the program memory, it has the least amount of reprogramming and therefore, must have the longest data retention and requires the lowest endurance (approximately 100,000 program/erase cycles). Conversely, the EEPROM, employed as data memory, must be able to be modified repeatedly and therefore must have higher endurance (more than 1 million program erase cycles). [0011] In order to achieve the one million program/erase cycles and have the single-byte erase segment, the traditional EEPROM employs a very large cell size (approximately 100 times the minimum feature size of the technology). [0012] Alternately, the flash memory can have a cell size that is significantly smaller (approximately 10 times the minimum feature size of the technology). [0013] In applications requiring high data rate change such as the data memory, as described, the nonvolatile memory requires a faster date change (program/erase) cycle. Thus the EEPROM requires a write or program speed of 1 ms. Alternately, the flash memory can tolerate a write speed that is on the order of 100 ms. [0014] FIGS. 1a-1d illustrates a floating gate memory cell of the prior art. The flash memory cell 10 is formed within a p-type substrate 2. An n.sup.+ drain region 6 and an n.sup.+ source region 4 are formed within the p-type substrate 2. [0015] A relatively thin gate dielectric or tunneling oxide 8 is deposited on the surface of the p-type substrate 2. A poly-crystalline silicon floating gate 12 is formed on the surface of the tunneling oxide 8 above the channel region 5 between the drain region 6 and source region 4. An interpoly dielectric layer 14 is placed on the floating gate 12 to separate the floating gate 8 from a second layer of poly-crystalline silicon that forms a control gate 16. [0016] In most applications of an EEPROM or flash memory, the p-type substrate 2 is connected to a substrate biasing voltage, which in most instances is the ground reference potential (0V). The source region 4 is connected to a source voltage generator through the source line terminal 22. The control gate 16 is connected through the word line terminal 20 to the control gate voltage generator. And the drain region 6 is connected through the contact 24 to the bit line and thus a bit line voltage generator. [0017] The memory cell 10 is separated from adjacent memory cells or circuits of an integrated circuit on a substrate by the shallow trench isolation 26. The shallow trench isolation 26 provides a level isolation from disturbing signals from any operations of the adjacent cells. [0018] As is well known, the coupling ratio of the control gate 16 and floating gate 12 are critical in determining the magnitude of voltage applied across the tunneling oxide 8 to cause the flow of charge to or from the floating gate 12. Thus it is desirable to maintain a relatively large coupling ratio for the floating gate 12. To accomplish this, the floating gate is extended over the shallow trench isolation 26 to form what is commonly termed "wings" 28. The "wings" 28 allow the voltages applied across the control gate 16 to be relatively lower and still allow the charges to flow to and from the floating gate 12. However, the "wings" prevent the design of the memory cell 10 from achieving a minimum size. [0019] According to conventional operation, the memory cell 10 is programmed by applying a relatively high voltage (on the order of 10V) to the control gate 16 through the word line 20. The drain voltage generator VD is set to a moderately high voltage (on the order of 5V), while the source voltage generator VS is set to the ground reference potential (0V). With these voltages hot electrons will be produced in the channel 5 near the drain region 6. These hot electrons will have sufficient energy to be accelerated across the tunneling oxide 8 and trapped on the floating gate 12. The trapped hot electrons will cause the threshold voltage of the field effect transistor (FET) that is formed by the memory cell 10 to be increased by three to five volts. This change in threshold voltage by the trapped hot electrons causes the cell to be programmed from the unprogrammed state of a logical one (1) to a logical zero (0). [0020] Conventionally, the memory cell is erased by setting the word line 20 to a relatively large negative voltage on the order of -18V. The bit line 18 and the source line 22 may be disconnected to allow the drain 6 and the source 4 to float. Alternately, the bit line 18 and the source line 22 are connected such that the drain 6 and the source 4 are connected to the ground reference voltage. Under these conditions there is a large electric field developed across the tunneling oxide 8 in the channel region 5. This field causes the electrons trapped in the floating gate 12 to flow to channel region 5, drain region 6 and source region 4. The electrons are then extracted from the floating gate 12 by the Fowler-Nordheim tunneling. This change in threshold voltage by the removal of the trapped hot electrons causes the cell to be erased (unprogrammed) state [0021] If the memory cell is to be written with a logical one (1), the cell is not programmed and no or little negative charges are placed on the floating gate 12. Thus, if the cell is erased, the relatively large negative voltage applied to the control gate 16 through the word line 20 causes the memory cell 10 to become over-erased. Positive charges actually are stored on the floating gate 12. This phenomenon causes the Field Effect Transistor (FET) of the memory cell 10 to become depletion-mode transistor and the drain 6 and the source 4 to become essentially shorted. When this occurs, the memory cell 10 causes false reading of data from a selected memory cell on a shared bit line of an array having an over-erased memory cell. To overcome this problem, a select gating transistor STx 30 is placed between the memory cell 10 and the source line 22, as shown in FIG. 2a-c. This prevents any excess current through the memory cell 10 when the select gating transistor STx 30 remains in the off-state. [0022] Refer now FIGS. 2a-2c for further discussion of the two transistor memory cell of the prior art. The memory cell 10 is formed within a p-type well 36 that is formed in an n-type well 34 on a p-type substrate 2. An n.sup.+ drain region 4 and an n.sup.+ source region 6 are formed within the p-type well 36. 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