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Nonvolatile semiconductor memory with x8/x16 operation mode using address controlNonvolatile semiconductor memory with x8/x16 operation mode using address control description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20060018180, Nonvolatile semiconductor memory with x8/x16 operation mode using address control. Brief Patent Description - Full Patent Description - Patent Application Claims
CROSS REFERENCE TO RELATED APPLICATIONS [0001] This application is a Continuation application of U.S. patent application Ser. No. 10/835,148, filed on 28 Apr. 2004. This application claims priority from Korean Patent Application No. 2003-39850, filed on Jun. 19, 2003, the contents of which are herein incorporated by reference in their entirety for all purposes. FIELD OF THE INVENTION [0002] The present invention generally relates to a flash memory (i.e., one of non-volatile semiconductor memories) devices and especially to NAND type flash memory devices capable of selectively controlling input/output of a data storage unit using addresses. BACKGROUND OF THE INVENTION [0003] A flash memory is capable of maintaining stored data without an external power supply. In addition, the flash memory can perform electrical erase and program operations freely even without additional refresh processes applied to the stored data. Since a NAND type flash memory has a string structure consisting of a plurality of flash memory cells connected in serial, the NAND type flash memory is suitable for a high integration and widely used in portable electronic apparatuses as a data storage. [0004] With rapidly increasing use of data requiring large storage capacity, such as motion pictures, voices and graphics, the NAND type flash memory having high integration density has been more widely used. [0005] The NAND type flash memory is characterized by several operation methods that draw clear line between flash memories and other memories apart from cell characteristics. One of the most critical characteristics for the NAND type flash memory in the ability to operate in the methods of a command preset and an address preset. [0006] According to the command preset method, commands that are combinations of predetermined bits (e.g., 00 h, 80 h, etc.) are inputted into a chip through an I/O pin to determine a next operation. According to the address preset method, an address to read or write data is inputted into the chip directly before starting an operation. [0007] The other memories such as SRAMs start to perform reading or writing operation of data as soon as an address and a clock for the operations are introduced. In contrast, the NAND type flash memory inputs a command to perform and an address into a chip using the above command preset method and the address preset method, and then performs the operation of reading or writing data if a clock is inputted. In the NAND type flash memory, there is clear interval between the time when data is inputted or outputted and the time when the address or command is introduced. Therefore, an input pin for introducing addresses or commands can be used in common with a data I/O pin. [0008] FIG. 1 is a block diagram illustrating a conventional .times.8 NAND type flash memory. [0009] As shown in FIG. 1, the conventional NAND type flash memory includes a memory cell array 100, a row selection circuit 101, a column selection circuit 103, a data latch circuit 102, a control circuit 104 and a data input/output circuit 105. The memory cell array 100 is a data storage, and the row selection circuit 101 selects a row of the memory cell array 100 according to row addresses A12 to A27. The column selection circuit 103 selects a column of the memory cell array 100 according to column addresses A0 to A11. The data latch circuit 102 latches the data of the memory cell array 100. The control circuit 104 controls operations inputting/outputting the data according to inputted clock signals nWE, nRE and nCE and control signals ALE, CLE and Command. [0010] Conventional NAND type flash memory comprises eight data I/O pins I/O0.about.I/O7 coupled to the data I/O circuit 105, a plurality of clock signal nWE, nRE, nCE input pins and control signal ALE, CLE input pins. The data I/O pins I/O0.about.I/O7 are used for inputting the command and the address A0.about.A27 and for inputting/outputting data. The clock signal nWE, nRE, nCE input pins control memory operations, and the control signal ALE, CLE input pins determine a kind of the data inputted into the data I/O pins I/O0.about.I/O7. The clock signal nWE is used for a synchronization of the addresses, commands and data introduced in the memory. The clock signal nRE is used for a synchronization at the time of data read out, and the clock signal nCE is used for selecting an operation of memory chip. The address latch enable (ALE) signal is a control signal used for identifying the data transferred through the data I/O pins I/O0.about.I/O7 as an address. The command latch enable (CLE) signal is a control signal used for identifying the data transferred through the I/O pins I/O0.about.I/O7 as a command. [0011] Conventionally, the command comprises 8-bits, such that the command may be inputted into the memory in one cycle, but the address comprises more than 8-bits, such that it is needed more than one cycle to input all the address as shown in the following Table 1. TABLE-US-00001 TABLE 1 Cycle I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 1st A0 A1 A2 A3 A4 A5 A6 A7 2nd A8 A9 A10 A11 L L L L 3rd A12 A13 A14 A15 A16 A17 A18 A19 4th A20 A21 A22 A23 A24 A25 A26 A27 [0012] The address A0.about.A11 in Table 1 is a column address for selecting a column of a memory cell array, and the address A12.about.A27 is a row address for selecting a raw. In addition, the signal introduced through the data I/O pins I/O4.about.I/O7 is usually set to a low level. [0013] Meanwhile, if the number of the I/O pins is increased to sixteen and the device operates at a .times.16 speed, data being inputted or outputted in parallel becomes doubled and the time (cycles) for processing the same number of data decreases to half. Therefore, efficiency of inputting/outputting data can be doubled over .times.8 operation. The following Table 2 describes inputs of the address when the memory operates at a .times.16 speed. TABLE-US-00002 TABLE 2 I/O 8.about. Cycle I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O 15 1st A0 A1 A2 A3 A4 A5 A6 A7 L 2nd A8 A9 A10 L L L L L L 3rd A11 A12 A13 A14 A15 A16 A17 A18 L 4th A19 A20 A21 A22 A23 A24 A25 A26 L [0014] As described in Table 2, even if the number of I/O pins is 16, only 8 pins I/O 0.about.I/O 7 are used for inputting the address. The I/O pins I/O 8.about.I/O 15 are used only in inputting/outputting data and usually set to a low level during the input of address. One (i.e., I/O 3 in second cycle) of the addresses used in the case of the .times.16 speed operation decreases compared to the case of the .times.8 speed operation because the number of data applied in serial decreases to half its number. [0015] As explained above, the .times.16 speed memory has double efficiency compared to the .times.8 speed memory. However, .times.8 or .times.16 memory is selectively used in a process of fabricating products according to functions and needs of the products regardless of the input/output efficiency. Therefore, most enterprises fabricating memories produce both of .times.8 and .times.16 memories. However, the .times.8 nonvolatile semiconductor memory and the x 16 nonvolatile semiconductor memory regime different fabrication processes. Therefore, the fabrication process may be inefficient. SUMMARY OF THE INVENTION [0016] It is therefore an aspect of embodiments of the invention to provide a nonvolatile semiconductor memory device for selectively determining the number of data bits inputted or outputted according to data rate option in one chip, and being capable of controlling data rate operation of the memory using addresses. [0017] In accordance with the present invention, a nonvolatile semiconductor memory device comprises a memory cell array divided into a plurality of blocks; a data latch circuit for latching a cell of a predetermined address with respect to each block in the memory cell array; a data I/O part including a plurality of I/O pins; a column address register for outputting addresses introduced from the data I/O part to a column selection circuit according to a synchronization signal; a data rate option selector for generating a data rate control signal according to a predetermined speed option; a block selector for generating a plurality of block selection signals to select each block of the memory cell array in response to a predetermined block selection address from the column addresses register and the data rate control signal; a column selection circuit for selecting a data line to input or output data in response to column selection addresses, the block selection signals and the data rate control signal; a data I/O controller for selecting a data line to input or output data from/to the column selection circuit in response to the block selection signals and the data rate control signal. BRIEF DESCRIPTION OF THE DRAWINGS [0018] FIG. 1 is a block diagram showing a conventional .times.8 speed NAND type flash memory. [0019] FIG. 2 is a block diagram showing a NAND type flash memory according to the invention having .times.8 or .times.16 data rate according to a predetermined data rate option. Continue reading about Nonvolatile semiconductor memory with x8/x16 operation mode using address control... Full patent description for Nonvolatile semiconductor memory with x8/x16 operation mode using address control Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Nonvolatile semiconductor memory with x8/x16 operation mode using address control patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. 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