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Nonvolatile semiconductor memory deviceNonvolatile semiconductor memory device description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20090268509, Nonvolatile semiconductor memory device. Brief Patent Description - Full Patent Description - Patent Application Claims
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2008-114799, filed on Apr. 25, 2008, the entire contents of which are incorporated herein by reference. 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device for nonvolatilely writing data in accordance with application of a voltage to a variable resistor. 2. Description of the Related Art In recent years, attention has been focused on a nonvolatile memory comprising memory cells each containing a variable resistor, which are connected at intersections of word lines and bit lines and arranged in matrix. Known examples of the nonvolatile memory of such the type include: a PCRAM (Phase-Change Random Access Memory) that uses a chalcogenide element as the variable resistor; a ReRAM (Resistance Random Access Memory) that uses a transition metal oxide element; and a CBRAM that changes the resistance by precipitating metal cations to form a bridge (conducting bridge) between electrodes and ionizing the precipitated metal to destruct the bridge. These resistance memories are characterized in that the variation in resistance is stored as information. The PCRAM utilizes the shape, such as the magnitude and the width, of a current/voltage pulse applied to the chalcogenide element to control the process from heating to cooling, thereby causing a phase change between the crystalline state and the amorphous state to control the resistance of the element (see Patent Document 1: JP 2002-541613T). The ReRAM includes the bipolar type and the unipolar type. In the case of the bipolar type, the direction of the current/voltage pulse applied to the transition metal oxide element is used to control the resistance of the element. On the other hand, in the case of the unipolar type, the magnitude and the width of the current/voltage pulse applied to the transition metal oxide element are used to control the resistance of the element. The unipolar type is preferable to realize a high-density memory cell array. This is because in the unipolar type a variable resistor and a rectifier such as a diode can be stacked at each cross-point of a bit line and a word line to configure a cell array with the use of no transistor. Such memory layers can be stacked to increase the memory capacity without increasing the area of the array. This is the purpose of a three-dimensional stacked resistance memory. In the case of the ReRAM of the unipolar type, data can be programmed in a resistance memory by applying a program voltage of around 6.0 V to the variable resistor for around 10 ns, thereby changing the variable resistor from a high-resistance state to a low-resistance state. This state change is referred to as “program” or “set”. When an erase voltage of around 2.0 V is applied to the data-programmed variable resistor and a flow of current of 1-10 μA is supplied for 200 ns to 1 μs, the variable resistor is changed from the low-resistance state to the high-resistance state. This state change is referred to as “erase” or “reset”. The resistance of such the variable resistor can be read out by applying a certain voltage to the variable resistor and sensing the value of current flowing in the variable resistor. Application of a voltage of 0.5 V to the variable resistor part requires application of a voltage, 0.5 V+Vf, to an actual bit line, which additionally includes a voltage Vf corresponding to the loss in the diode. This bit line voltage is generated by applying a clamp voltage to the gate of a clamp transistor in a sense amplifier circuit. The clamp voltage is generated from a bit line clamp voltage generator circuit. The diode loss Vf has temperature dependence. Accordingly, if the clamp voltage and finally the bit line voltage have no temperature dependence, the voltage applied to the variable resistor part has temperature dependence instead. Therefore, even in the same variable resistor, the current flowing in the variable resistor part varies depending on the temperature and shifts the 1/0 decision point on sensing, which reduces the sense margin as a problem. In an aspect the present invention provides a nonvolatile semiconductor memory device, comprising: a memory cell array including first and second mutually crossing lines and electrically erasable programmable memory cells arranged at intersections of the first and second lines, each memory cell containing a variable resistor operative to nonvolatilely store the resistance thereof as data and a first non-ohmic element operative to switch the variable resistor; and a clamp voltage generator circuit operative to generate a clamp voltage required for access to the memory cell and applied to the first and second lines. The clamp voltage generator circuit has a temperature compensation function of compensating for the temperature characteristic of the first non-ohmic element. In another aspect the present invention provides a nonvolatile semiconductor memory device, comprising: a memory cell array including first and second mutually crossing lines and electrically erasable programmable memory cells arranged at intersections of the first and second lines, each memory cell containing a variable resistor operative to nonvolatilely store the resistance thereof as data and a first non-ohmic element operative to switch the variable resistor; a sense amplifier containing a clamp transistor operative to clamp a voltage required for access to the memory cell and applied to the first or second line; and a clamp voltage generator circuit operative to generate a clamp voltage to control the clamp transistor. The clamp voltage generator circuit includes a variable resistor circuit operative to set a voltage applied to the variable resistor on access to the memory cell, and a second non-ohmic element operative to compensate for the temperature characteristic of the first non-ohmic element. In yet another aspect the present invention provides a nonvolatile semiconductor memory device, comprising: a memory cell array including first and second mutually crossing lines and electrically erasable programmable memory cells arranged at intersections of the first and second lines, each memory cell containing a variable resistor operative to nonvolatilely store the resistance thereof as data and a first non-ohmic element operative to switch the variable resistor; and a clamp voltage generator circuit operative to generate a clamp voltage required for access to the memory cell and applied to the first and second lines. The clamp voltage generator circuit has a temperature compensation function of compensating for the temperature characteristic of the non-ohmic element and is formed in the same layer as that of the memory cell accessible with the clamp voltage generation. Continue reading about Nonvolatile semiconductor memory device... Full patent description for Nonvolatile semiconductor memory device Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Nonvolatile semiconductor memory device patent application. Patent Applications in related categories: 20090279343 - Operating method of electrical pulse voltage for rram application - Metal-oxide based memory devices and methods for operating and manufacturing such devices are described herein. A method for manufacturing a memory device as described herein comprises forming a metal-oxide memory element, and applying an activating energy to the metal-oxide memory element. In embodiments the activating energy can be applied by ... 20090279343 - Operating method of electrical pulse voltage for rram application - Metal-oxide based memory devices and methods for operating and manufacturing such devices are described herein. A method for manufacturing a memory device as described herein comprises forming a metal-oxide memory element, and applying an activating energy to the metal-oxide memory element. In embodiments the activating energy can be applied by ... 20090279344 - Resistance change memory device - A resistance change memory device includes: a memory cell formed of a variable resistance element and a diode connected in series, the state of the variable resistance element being reversibly changed in accordance with applied voltage or current; and a stabilizing circuit so coupled in series to the current path ... 20090279344 - Resistance change memory device - A resistance change memory device includes: a memory cell formed of a variable resistance element and a diode connected in series, the state of the variable resistance element being reversibly changed in accordance with applied voltage or current; and a stabilizing circuit so coupled in series to the current path ... 20090279345 - Resistive memory element sensing using averaging - A system for determining the logic state of a resistive memory cell element, for example an MRAM resistive cell element. The system includes a controlled voltage supply, an electronic charge reservoir, a current source, and a pulse counter. The controlled voltage supply is connected to the resistive memory cell element ... 20090279345 - Resistive memory element sensing using averaging - A system for determining the logic state of a resistive memory cell element, for example an MRAM resistive cell element. The system includes a controlled voltage supply, an electronic charge reservoir, a current source, and a pulse counter. The controlled voltage supply is connected to the resistive memory cell element ... ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. 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