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Nonvolatile semiconductor memory and fabrication method thereforRelated Patent Categories: Semiconductor Device Manufacturing: Process, Making Device Array And Selectively Interconnecting, With Electrical Circuit LayoutNonvolatile semiconductor memory and fabrication method therefor description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20070224736, Nonvolatile semiconductor memory and fabrication method therefor. Brief Patent Description - Full Patent Description - Patent Application Claims
CROSS REFERENCE TO RELATED APPLICATIONS [0001] This application is a continuation of and claims the benefit of priority under 35 U.S.C. .sctn.120 from U.S. Ser. No. 10/892,445, filed Jul. 16, 2004, and claims the benefit of priority under 35 U.S.C. .sctn. 119 from Japanese Patent Application P2003-285015 filed on Aug. 1, 2003; the entire contents of each application are incorporated by reference herein. BACKGROUND OF THE INVENTION [0002] 1. Field of the Invention [0003] The present invention relates to a nonvolatile semiconductor memory and a fabrication method for the device. In particular, the invention relates to a nonvolatile semiconductor memory and a fabrication method that achieves a highly integrated circuit where two memory cell columns share a single bit line. [0004] 2. Description of the Related Art [0005] As an example of conventional technology, a NAND EEPROM has a single bit line for each NAND column. When bit line BLk is a write-in bit line, and bit lines BLk+1 and BLk-1 are write-in control bit lines, respectively, during write-in, a predetermined gate voltage Vsg is applied to a bit line BL side select gate transistor SG1, and a sufficiently low voltage VBLpgm is applied to a bit line BL that is utilized to write-in. The aforementioned gate voltage Vsg is set to a voltage that allows the select gate transistor SG1 to turn on as opposed to the low voltage VBLpgm. A sufficiently high voltage VBLinhibit is applied to the bit lines BLk+1 and BLk-1 that are utilized to control write-in. The voltage VBLinhibit is set to a voltage level that sufficiently allows the aforementioned select gate transistor SG1 to turn off. A NAND memory cell transistor utilized by a corresponding bit line BL for write-in that has received a sufficiently low voltage VBLpgm is written when the select gate transistor SG1 is turned on so as to apply VBLpgm to the memory cell transistor. Thus, the channel voltage for the memory cell transistor is sufficiently reduced. Also, a NAND memory cell transistor utilized by corresponding bit lines BLk+1 and BLk-1 to control write-in that has received a sufficiently high voltage VBLinhibit is not written when the select gate transistor SG1 is turned off because the memory cell transistor channel voltage rises through capacitive coupling with a control gate CG. This state is a write-in controlled state, as disclosed by K. Imamiya, et. al., "A 125 mm.sup.2 1 Gb NAND Flash Memory With 10 M Bytes/s Program Speed", IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 37, NO. 11, NOVEMBER 2002, pp. 1493-1501 [0006] However there is a problem in the conventional technology. When the device region pitch of NAND memory cell transistors is 2F, the size of the contact connecting the bit line BL to the diffusion layer of the bit line BL side select gate transistor must be larger than F considering misalignment and largely depending on exposure techniques. Here, F denotes the minimum processing dimension. Therefore, the interval between adjacent bit line contacts CB connecting neighboring bit lines BL to the respective diffusion layers of the bit line BL side select gate transistors is less than F. Accordingly, there is a large probability of an electrical short circuit will occur. Naturally, since each bit line BL has to be connected to corresponding bit line contact CB, which is used to connect the diffusion layer of a bit line BL side select gate transistor, processing of the bit lines and contacts is extremely difficult. [0007] The present invention provides a nonvolatile semiconductor memory and a fabrication method for the device, which allow high integration of a NAND EEPROM, and allows bit line contacts CB, each connecting a bit line BL to the diffusion layer of a bit line BL side select gate transistor, to be arranged with a pitch that is twice the NAND column pitch, where two NAND columns share a single bit line BL, particularly in NAND EEPROM. SUMMARY OF THE INVENTION [0008] An aspect of the present invention inheres in a nonvolatile semiconductor memory including: (a) first and second memory cell columns, each having a plurality of memory cell transistors connected in series, each of the memory cell transistors has a gate structure including a floating gate and first and second control gates located at both sides of the floating gate; (b) a first select gate transistor connected between the first memory cell column and a bit line; (c) a second select gate transistor connected between the second memory cell column and the bit line; and (d) bit line contacts connecting the bit line to a diffusion layer of the first and second select gate transistors provided at a pitch twice the pitch of the memory cell column. [0009] Another aspect of the present invention inheres in a fabrication method for a nonvolatile semiconductor memory including: (a) forming gate insulating films for a memory cell transistor and a select gate transistor on a semiconductor substrate; (b) forming a floating gate for the memory cell transistor and a gate electrode for the select gate transistor; (c) forming a cap insulating film for the floating gate; (d) forming a device isolating region; (e) depositing an inter-gate insulating film between the floating gate and control gates for the memory cell transistor; (f) forming a control gate for the memory cell transistor and a gate interconnect for the select gate transistor; (g) forming a salicide control insulating film across the entire surface of the device; and (h) selectively removing the salicide control insulating film on the control gate and on an exposed surface of the semiconductor substrate. [0010] Another aspect of the present invention inheres in a fabrication method for a nonvolatile semiconductor memory including: (a) depositing and forming on a semiconductor substrate a gate insulating film for a memory cell transistor, a control gate, and a mask insulating film; (b) forming a device isolating region and etching the semiconductor substrate so as to form a portion for forming a floating gate; (c) carrying out a heat treatment; (d) depositing a inter-gate insulating film between a control gate and a floating gate; (e) forming a channel profile for the memory cell transistor; (f) opening a tunnel insulating film formation portion; (g) forming a tunnel insulating film for the memory cell transistor; (h) depositing a floating gate electrode across the entire surface of the device; (i) decreasing the height of the floating gate by etch back techniques; (j) forming a cap insulating film across the entire surface of the device, and exposing only the control gate electrode; (k) selectively etching the control gate electrode film; (l) depositing a first interlayer insulating film across the entire surface of the device; (m) exposing only the control gate electrode; (n) selectively etching the cap insulating film within a first opening region so as to expose the floating gate electrode; (o) decreasing the height of the upper surface of the control gate electrode by etching techniques; (p) forming a sidewall insulating film across the entire surface of the device; and (q) forming an opening narrower than the gate width on the upper surface of the floating gate. [0011] Another aspect of the present invention inheres in a fabrication method for a nonvolatile semiconductor memory including: (a) forming a tunnel insulating film, a first gate electrode film for a select gate transistor, and a cap insulating film on the first gate electrode film on a semiconductor substrate; (b) processing each of the films by lithography and etching; (c) depositing an inter-gate insulating film between the first gate electrode and a region intended for forming a control gate across the entire surface of the substrate; (d) removing the inter-gate insulating film at sidewall surface of the first gate electrode by lithography and etching; and (e) depositing a gate electrode film as a control gate and select gate transistor gate interconnect across the entire surface of the substrate, and electrically contacting the first gate electrode and the gate electrode film. BRIEF DESCRIPTION OF DRAWINGS [0012] FIG. 1A is a schematic circuit diagram of a nonvolatile semiconductor memory according to a first embodiment of the present invention; [0013] FIG. 1B is a schematic device cross-sectional block diagram cut along a line IV-IV in FIG. 2B and corresponds to FIG. 1A; [0014] FIG. 2A is a schematic circuit diagram of the nonvolatile semiconductor memory according to the first embodiment of the present invention; [0015] FIG. 2B is a top view of a schematic device pattern corresponding to FIG. 2A; [0016] FIG. 3A is a schematic device cross-sectional block diagram of the nonvolatile semiconductor memory according to the first embodiment of the present invention, and is a cross-sectional configuration cut along I-I of FIG. 2B; [0017] FIG. 3B is a cross-sectional configuration cut along II-II of FIG. 2B; [0018] FIG. 3C is a cross-sectional configuration cut along III-III of FIG. 2B; [0019] FIG. 4 is a schematic matrix circuit diagram of the nonvolatile semiconductor memory according to the first embodiment of the present invention; [0020] FIG. 5A is a diagram showing operation waveforms when writing to a specific memory cell in NAND column 3 of FIG. 4; Continue reading about Nonvolatile semiconductor memory and fabrication method therefor... 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