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  Non-volatile semiconductor storage deviceUSPTO Application #: 20080019162Title: Non-volatile semiconductor storage device Abstract: This non-volatile semiconductor storage device includes a flip-flop in which two inverters, each consisting of a load transistor and a storage transistor connected in series, are cross-connected; and two gate transistors, each respectively connected to a node of the flip-flop on a side thereof. The storage transistors of the inverters are constituted by storage transistors which can be threshold voltage controlled by injection of electrons into the neighborhood of their gates. This non-volatile semiconductor storage device further includes two bit lines, each of which is connected to a respective one of the two gate transistors; a word line which is connected to both of the gate electrodes of the two gate transistors; a first voltage supply line which is connected to the sources of the storage transistors of the inverters; and a second voltage supply line which is connected to the sources of the load transistors of the inverters. (end of abstract)
Agent: Mark D. Saralino (general) Renner, Otto, Boisselle & Sklar, LLP - Cleveland, OH, US Inventors: Taku OGURA, Masaaki Mihara, Yoshiki Kawajiri USPTO Applicaton #: 20080019162 - Class: 365 72 (USPTO) The Patent Description & Claims data below is from USPTO Patent Application 20080019162. Brief Patent Description - Full Patent Description - Patent Application Claims
CROSS REFERENCE [0001]This Nonprovisional application claims priority under 35 U.S.C. .sctn. 119(a) on Patent Application No. 2006-199673 filed in Japan on Jul. 21, 2006, the entire contents of which are hereby incorporated by reference. BACKGROUND OF THE INVENTION [0002]The present invention relates to a non-volatile semiconductor storage device which can be electrically erased and written, to a state determination method for such a semiconductor storage device, and to a semiconductor integrated circuit device incorporating such a semiconductor storage device. [0003]Along with increase of internal SRAM capacity, the necessity has increased for providing redundancy, for performing individual tuning after making boards such as LCD drivers and the like, and for low cost fuses which are being demanded along with the great increase in various types of application which involve personal identification information (ID codes, encryption and decryption keys, numbers of IC cards, and the like). [0004]In the prior art, as fuse elements which can be made with a standard CMOS process, there is a known one in which a polysilicon or metal wiring layer is blown out by a laser or an electrical current, a known one in which an insulating gate layer or the like is destroyed by voltage, and the like. However, such a fuse which employs such a blowing out or insulation destruction method or the like is not suitable for the application described above, since it can only be programmed once. [0005]On the other hand, in the case of using a non-volatile element of the floating gate type which can be manufactured by a CMOS process, although it is possible to implement a fuse which can be electrically erased and written, introduction of a special process for making the transistors non-volatile, such with a prior art type flash memory, is not appropriate from the point of view of cost. Furthermore, with a floating gate type element made with a standard CMOS process, there has been the problem that the data storage characteristics deteriorate as the insulating layer becomes thinner along with increase of the integration scale. [0006]Thus in, for example, U.S. Pat. No. 6,518,614, Japanese Laid-Open Patent Publication 2004-56095, and Japanese Laid-Open Patent Publication 2005-353106, there are disclosed a non-volatile storage device which can be manufactured by a standard CMOS process, and a non-volatile storage device which does not have any special floating gates. [0007]FIG. 1 is a figure showing the memory cell structure of a non-volatile storage device which has been manufactured by a standard CMOS process, as disclosed in Japanese Laid-Open Patent Publication 2005-353106. Fundamentally, this consists of N-type MOS transistors MCN1 and MCN2 which constitute a non-volatile data storage unit, and a flip-flop unit (MN3, MN4, MP1, and MP2) of a static latch type which takes the output nodes T and B of the non-volatile data storage unit as differential inputs. In this flip-flop unit, normal reading out and writing SRAM operation is performed. Furthermore, it is possible to reload the information of the non-volatile data storage unit and to store data in the flip-flop unit. [0008]FIG. 2 show the data setting method. This data setting method is a method in which the data is determined by the voltage difference between the threshold values of the two N-type MOS transistors MCN1 and MCN2. In the initial state (FIG. 2A) before writing data, the N-type MOS transistors MCN1 and MCN2 both have the threshold voltage Vth, and, in this state, the output data of the flip-flop is indeterminate. In order to determine the data, first, writing of the data to "0" is performed (FIG. 2B). This writing is implemented by raising the threshold voltage on the side of MCN1 to Vth1 (where Vth1>Vth0). With this structure, it is not possible to perform erasure (reduction of Vth). Because of this, subsequent writing of the data "1" from the data "0" state is implemented by raising the threshold voltage on the side of MCN2 to Vth2 (where Vth2>Vth1) (FIG. 2C). [0009]FIG. 3 shows the method for changing the threshold voltages of the N-type MOS transistors of the above described non-volatile data storage unit. In FIG. 3, the data "0" case is shown, i.e. the case in which the threshold voltage on the side of MCN1 is raised. Fundamentally, positive advantage is taken of the deterioration characteristic of an N-type MOS transistor due to hot carriers. In other words, it is arranged to set to 0 V the source potential of that transistor MCN1 whose threshold voltage it is desired to raise, to set its gate potential (MLW) to 2.5 V, and to set its drain potential (the node T) to 5V, thereby raising its threshold voltage in the vicinity of its drain terminal by the hot carrier injection phenomenon. At this time, in order for the potential of the bit line BLT to be sufficiently supplied to the node T, it is necessary to raise the potential of BLT to 5 V, and to raise the potential of the word line WL of the flip-flop unit to 7V. As for that transistor MCN2 whose threshold voltage it is not desired to raise, by setting the potential of BLB to 0 V, it is arranged for hot carrier injection not to take place in the vicinity of the drain terminal of that transistor MCN2. And, when writing the data "1", since the threshold voltage on the side of MCN2 is be raised, BLT is set to 0 V and BLB is set to 5 V. The other conditions are the same as when writing the data "0". [0010]FIG. 4 shows the method for transferring data transfer from the non-volatile data storage unit to the flip-flop unit. This figure shows the data transfer method in the data "0" case, in other words when the threshold voltage Vth1 of MCN1 is higher than the threshold voltage Vth0 of MCN2. In the state of the flip-flop unit in which the word line WL=0 V and a restore control signal RESTORE=0 V, by lowering an equalization control signal ZEQ from Vcc to 0 V at the time instant T0, the node T and the node B are equalized at the same potential. This equalization operation ends at the time instant T1. And MLW, which is the gate potential of the transistors MCN1 and MCN2, is gradually raised from the time instant T2. When this is done, MCN2 is turned ON first, being that transistor whose threshold voltage is the lower, and the potential at the node B is pulled down. Although MCN1 also goes ON after some time, finally the latch is established in the state in which the node B on the side of the transistor MCN2 whose threshold voltage is the lower has reached 0 V, while the node T on the side of the transistor MCN1 has reached Vcc. And the rising of MLW is completed at the time instant T3. By raising RESTORE from 0 V to Vcc at the time instant T4, the latching of the flip-flop unit is activated, and the data is held in a stable manner. Finally, at the time instant T5, MLW reaches 0 V and this process terminates. [0011]While the operation of such a memory cell is as described above, there are the following problems with this structure. [0012](1) The margin of threshold voltage difference is small. [0013]Vth1-Vth0 corresponds to this threshold voltage difference margin in the case of the data "0", and Vth2-Vth1 in the case of the data "1". To some extent, there is an upper limit value Vth_max for the amount of change of the threshold voltage due to the hot carrier injection phenomenon. If the margin is allocated equally between reading out the data "0" and the data "1", then, if it is supposed that rewriting is performed once, the margin for each becomes (Vth_max-Vth0)/2. And, if it is supposed that rewriting is performed N times, then taking the maximum value of Vth_control as Vth_max, it must be divided into 2N portions, and the margin of each of the data "0" and the data "1" becomes (Vth_max-Vth0)/2N, so that the margin becomes yet smaller. [0014](2) As operating voltages when writing data into this non-volatile data storage unit, it is necessary to apply high voltages (7 V and 5 V) to the word line WL and to the bit lines BLT and BLB for each memory cell which it is necessary to control. This means that it is necessary to use high withstand voltage transistors for the drivers which drive the word lines and the bit lines, and for the column selection transistors for selecting the bit lines. Since the performance with high withstand voltage transistors, which are optimized for high voltage, is deteriorated when operating at Vcc=1.8 V as during normal reading out operation, accordingly the problem occurs that this entails access delay. And increasing the size of the transistors in order to increase the current drive capability causes the accompanying problem that the chip area becomes large. [0015]One object of the present invention is to provide a rewritable non-volatile semiconductor storage device, with which it is possible to make the reading out margin large. [0016]A further object of the present invention is to provide a rewritable non-volatile semiconductor storage device, with which it is possible to perform control of the word lines and the bit lines at the Vcc level. [0017]Other objects of the present invention are to provide a state determination method for such a semiconductor storage device, and to provide a semiconductor integrated circuit device incorporating such a semiconductor storage device. SUMMARY OF THE INVENTION [0018]The non-volatile semiconductor storage device of the present invention includes a flip-flop in which two inverters, each consisting of a load transistor and a storage transistor connected in series, are cross-connected; and two gate transistors, each respectively connected to a node of said flip-flop on a side thereof. [0019]Furthermore, the non-volatile semiconductor storage device of the present invention includes two bit lines, each of which is connected to a respective one of said two gate transistors, and a word line which is connected to both of the gate electrodes of said two gate transistors. These two bit lines and this word line are controlled to a voltage between operating power supply voltage and ground voltage. [0020]Moreover, the non-volatile semiconductor storage device of the present invention includes a first voltage supply line which is connected to the sources of said storage transistors of said inverters, and a second voltage supply line which is connected to the sources of said load transistors of said inverters. A predetermined first voltage is supplied to the first voltage supply line during writing and during erasure. And a predetermined second voltage is supplied to the second voltage supply line during writing. This predetermined first voltage and this predetermined second voltage may be, for example, high voltages greater than or equal to the operating power supply voltage. [0021]These storage transistors are constituted by storage transistors which can be threshold voltage controlled by injection of electrons into the neighborhood of their gates. In the non-volatile semiconductor storage device described above, the writing and erasure of data are implemented by controlling the threshold voltages of the storage transistors. These threshold voltages are provided via the first voltage supply line and the second voltage supply line which are connected to the two ends of the two inverters (the sources of the load transistors and the sources of the storage transistors). Continue reading... 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