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  Non-volatile memoryUSPTO Application #: 20070120151Title: Non-volatile memory Abstract: A NVM including a substrate, a control gate layer, a charge storage layer, a tunneling layer, a charge barrier layer, a gate dielectric layer and a first doping region is described. The control gate layer is disposed in a first trench of the substrate; the charge storage layer is disposed between the sidewall of the first trench and the control gate layer; the tunneling layer is disposed between the sidewall of the first trench and the charge storage layer; the charge barrier layer is disposed between the charge storage layer and the control gate layer; the gate dielectric layer is disposed between the bottom of the first trench and the control gate layer; and the first doping region is disposed in the substrate at one side of the control gate layer. (end of abstract) Agent: Jianq Chyun Intellectual Property Office - Taipei, TW Inventor: Ting-Sing Wang USPTO Applicaton #: 20070120151 - Class: 257213000 (USPTO) Related Patent Categories: Active Solid-state Devices (e.g., Transistors, Solid-state Diodes), Field Effect Device The Patent Description & Claims data below is from USPTO Patent Application 20070120151. Brief Patent Description - Full Patent Description - Patent Application Claims
CROSS-REFERENCE TO RELATED APPLICATION [0001] This is a divisional application of Patent Application No. 11/161,724, filed on Aug. 15, 2005, which claims the priority benefit of Taiwan patent application serial no. 94118693, filed on Jun. 7, 2005 and is now pending. The entirety of each of the above-mentioned patent applications is hereby incorporated by reference herein and made a part of this specification. BACKGROUND OF THE INVENTION [0002] 1. Field of Invention [0003] The present invention relates to a memory device, and particularly to a non-volatile memory (NVM). [0004] 2. Description of the Related Art [0005] Non-volatile memories (NVMs) can be written, erased and retain data after power is off. In addition, NVMs have other advantages such as small size, fast access speed and low electricity consumption. Since data is erased "block by block", the operation speed of NVMs is fast. Therefore, the NVM has become a memory device widely applied in PC and various electronic devices. [0006] A NVM comprises a plurality of memory cells (MCs) arranged in an array. Wherein, each MC is formed by a tunneling layer, a charge storage layer, a charge barrier layer and a control gate layer stacked in sequence. Besides, at both sides of the gate in the substrate are disposed with two doping regions serving as a source region and a drain region, respectively. [0007] As data is written into the memory, a bias voltage is applied to the control gate layer, the source region and the drain region to inject electrons into the control gate layer. When data is read from the memory, an operation voltage is applied to the control gate layer. The charging status of the charge storage layer affects the switching on/off status of the channel underneath, which serves to determine the "0" or "1" of the data value. While data in the memory is erased, the relative voltage levels of the substrate, the source region, the drain region or the control gate layer are increased, so that the electrons in the charge storage layer penetrate through the tunneling layer into the substrate by a tunneling effect. The erasing method is usually termed as "substrate erase". [0008] Note that although the IC develops towards higher integrity and minimal size, yet along with larger application software today, the required memory capacity is accordingly bigger. To adapt such challenge where a memory is required to have a smaller size with a bigger capacity, the conventional memory cell (MC) structure and the fabrication method thereof must be modified and updated. In fact, it has been an important topic in the deep sub-micron (DSM) technology to enhance the level of integration while keeping the original memory capacity in a limited space. SUMMARY OF THE INVENTION [0009] Accordingly, an object of the present invention is to provide a fabrication method of non-volatile memories (NVMs) for enhancing the level of integration. [0010] Another object of the present invention is to provide a non-volatile memory (NVM), wherein a single memory unit is able to serve as a multi-stage MC. [0011] The present invention provides a fabrication method of NVMs. In the process, a substrate is provided. Next, in the substrate, a plurality of first trenches and a plurality of second trenches are formed, and the second trenches are located above and across the first trenches. A tunneling layer and a charge storage layer are sequentially formed on the sidewall of each of the second trenches. Further, an isolation layer is filled into each of the first trenches. A charge barrier layer is formed on the sidewall of each the second trench to cover the corresponding charge storage layer. Besides, a gate dielectric layer is formed on the bottom of each of the second trenches, and the gate dielectric layer covers at least a partial substrate between two adjacent first trenches. A control gate layer is filled into each of the second trenches. A plurality of first doping regions are formed in the substrate at both sides of the control gate layer. [0012] According to the fabrication method of NVMs in the embodiments of the present invention, after forming the gate dielectric layer, the method further includes forming a plurality of second doping regions on the bottom of each second trench. Moreover, before forming the second doping regions, an isolation spacer may be formed on each charge barrier layer located on the sidewall of each second trench. To form the isolation spacer, a spacer material layer is formed in each of the second trenches, then the spacer material layer is anisotropically etched. [0013] According to the fabrication method of NVMs in the embodiments of the present invention, the method for forming the aforementioned first trenches and second trenches is, for example, by using a first patterned mask to form the second trenches, which are extended in a first extension direction, and then using a second patterned mask to form the second trenches in a second extension direction. The first extension direction crosses the second extension direction and the depth of the first trench is deeper than that of the second trench. [0014] According to the fabrication method of NVMs in the embodiments of the present invention, the method for filling the above-described isolation layer into the first trench is by, for example, forming an isolation material layer on the substrate, and then a chemical mechanical polish (CMP) process is performed for removing partial isolation material layer outside the second trench until a portion of the substrate between two adjacent second trenches is exposed. Further, an etching process is performed for removing the partial isolation material layer in the second trench until the bottom of the second trench and partial substrate between two adjacent first trenches are exposed. [0015] The present invention provides a NVM, which comprises a substrate, a control gate layer, a charge storage layer, a tunneling layer, a charge barrier layer, a gate dielectric layer and a first doping region. Wherein, the control gate layer is disposed in a first trench of the substrate; the charge storage layer is disposed between the sidewall of the first trench and the control gate layer; the tunneling layer is disposed between the sidewall of the first trench and the charge storage layer; the charge barrier layer is disposed between the charge storage layer and the control gate layer; the gate dielectric layer is disposed between the bottom of the first trench and the control gate layer; and the first doping region is disposed in the substrate at one side of the control gate layer. [0016] According to the embodiments of the present invention, the NVM further includes a second doping region disposed on the bottom of the first trench. [0017] According to the embodiments of the present invention, the NVM further includes an isolation spacer disposed between the charge barrier layer on the sidewall of the first trench and the control gate layer. [0018] According to the embodiments of the present invention, the NVM further includes an isolation layer disposed in a second trench of the substrate. Wherein, the first trench is located across and above the second trench. [0019] According to the embodiments of the present invention, the depth of the above-mentioned second trench is deeper than that of the first trench. [0020] In the NVM of the present invention, if no second doping region and isolation spacer are disposed, each of the charge storage layers located at both sides of each memory unit in the trench is used for storing 1-bit. In other words, one memory unit has one memory cell, which can store 2-bit. If a second doping region is disposed, the second doping region is used as a source/drain region; thus, each memory unit in the trench has two memory cells located at both sides of the trench and the charge storage layer of each memory cell can be used for storing 1-bit. Therefore, a memory unit can be used as a multi-stage memory cell. Besides, the thickness of the corresponding isolation spacer can be used to control the width of a second doping region. Further, the arrangement manner of the memory units according to the present invention also makes effective use of a wafer space, increasing the device integration level. Moreover, the process is simpler. BRIEF DESCRIPTION OF THE DRAWINGS Continue reading... Full patent description for Non-volatile memory Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Non-volatile memory patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. 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