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  Non-volatile memory array with simultaneous write and erase featureUSPTO Application #: 20060187707Title: Non-volatile memory array with simultaneous write and erase feature Abstract: A non-volatile transistor memory array, having individual cells, each individual cell having a current injector transistor and a non-volatile memory transistor. Injector current gives rise to charged particles that can be stored in the memory transistor by tunneling. When a row of the array is activated by a word line, the active row has current injectors ready to operate if program line voltages are appropriate to cause charge storage in a memory cell, while a cell in an adjacent row is erased by charge being driven from a memory transistor. A series of conductive plates are arranged in capacitive relation to the word line, with each plate having a pair of oppositely extending tangs, one allowing programming of a cell in a first row and another allowing erasing of a cell in another row. (end of abstract)
Agent: Schneck & Schneck - San Jose, CA, US Inventor: Bohumil Lojek USPTO Applicaton #: 20060187707 - Class: 365185010 (USPTO) The Patent Description & Claims data below is from USPTO Patent Application 20060187707. Brief Patent Description - Full Patent Description - Patent Application Claims
CROSS-REFERENCE TO RELATED APPLICATION [0001] This is a divisional of pending U.S. patent application Ser. No. 10/773,059, filed Feb. 4, 2004 and entitled "NON-VOLATILE MEMORY ARRAY WITH SIMULTANEOUS WRITE AND ERASE FEATURE," incorporated herein by reference. TECHNICAL FIELD [0002] The invention relates to non-volatile memory arrays and, in particular, to a non-volatile memory array adapted for a simultaneous write and erase. BACKGROUND ART [0003] Impact ionization has been known for several years. U.S. Pat. No. 4,432,075 to B. Eitan and U.S. Pat. No. 4,821,236 to Hayashi et al. describe an EEPROM transistor adjacent to a charge generator, creating a substrate current near the EEPROM, creating excess charge or holes, resembling space charge, near subsurface electrodes of the EEPROM. Assume that the holes are generated and accelerated toward one of the electrodes of the EEPROM. Resulting secondary electrons are sufficiently energetic to penetrate gate oxide over the substrate and become injected into a conductive floating gate. For very small EEPROMs, the floating gate becomes charged by band-to-band tunneling, a situation which eliminates the need for a control gate over the floating gate. [0004] U.S. Pat. No. 5,126,967 and U.S. Pat. No. 4,890,259 to R. Sinks describe a memory array made of non-volatile transistors that can store analog waveforms. [0005] The ability of EEPROM transistors to directly record analog waveforms, without A-to-D conversion, gives rise to new applications, such as use in neural networks. This has been pointed out in U.S. Pat. No. 6,125,053 where C. Dioris and C. Mead describe use of EEPROMs storing variable amounts of charge generated by impact ionization to represent an analog value. This is in contrast to a conventional EEPROM where a floating gate either stores charge or does not store charge, thereby indicating a digital value. In the '053 patent, an EEPROM is described that permits simultaneous writing and reading. [0006] An analogous problem is simultaneous programming and erasing operations in an array. An object of the invention was to devise a memory array that has simultaneous programming of one memory region and erasing of another memory region. SUMMARY OF THE INVENTION [0007] The above object has been met with semiconductor non-volatile memory array having cells in one row that can be written while cells in another row are erased. The cells feature a non-volatile memory transistor of the type having a floating gate, plus a charge injector formed in an isolated but adjacent isolation area, plus customary row and column address lines. The charge injector creates space charge flowing toward the bottom of the substrate below isolation regions. Because of proximity of the injector to the memory transistor, one or more of the electrodes of the memory transistor is biased to attract charge, e.g. holes. Impacts of the holes upon the charged electrode or electrodes gives rise to secondary particles, specifically electrons, by impact ionization, having sufficient energy for injecting onto the floating gate. Current stimulation in the injector, a fast diode, and electrode bias in the transistor, in a carefully controlled manner leads to placement of precise amounts of charge on the floating gate. A current meter placed at an electrode may or could measure the transferred charge over a particular range, out of several possible ranges, determined by substrate and injector region doping. Different doping levels give rise to different conduction thresholds for memory cells in the transistor and hence different ranges. The different thresholds in a transistor array allow an array to act over an extended range of analog signal trimming, without analog-to-digital conversion. [0008] To achieve simultaneous writing and erasing, a row being currently written is selected by a word line, while the same line erases an adjacent, non-current row. The word line is spaced by dielectric material from a plurality of polysilicon plates, the spacing creating a capacitive relation relative to the word line. The poly plates have tangs that form control gates of transistors. Tangs extending in one direction form EEPROM control gates for writing in one row while tangs extending in another direction form control gates for erasing in another row. BRIEF DESCRIPTION OF THE DRAWINGS [0009] FIG. 1 is a circuit diagram of a portion of a non-volatile transistor memory array in accordance with the present invention. [0010] FIG. 2 is a redrawn schematic drawing of a memory cell shown in the memory array of FIG. 1. [0011] FIG. 3 is a sectional view of a memory cell in the memory array of FIG. 1, taken along lines 3-3 of FIG. 4. [0012] FIG. 4 is a top view of a chip layout of a memory cell shown in FIG. 2. [0013] FIG. 5 is a plot of injector current versus voltage in a band-to-band tunneling operating area contrasted with an avalanche breakdown area for a transistor memory cell of the kind shown in FIG. 2. [0014] FIG. 6 is a plot of injector current as a function of drain and control gate voltage bias for a transistor memory cell of the kind shown in FIG. 2. [0015] FIG. 7 is a plot of number of electrons stored as a function of threshold voltage for memory cells of the kind shown in FIG. 2. [0016] FIG. 8 is a sectional view of a word line in a memory cell in the memory array of FIG. 1, taken along lines 8-8 of FIG. 4. DETAILED DESCRIPTION OF THE INVENTION [0017] With reference to FIG. 1, a first memory cell 15 of a non-volatile transistor memory array has first and second programming lines 11 and 13, associated with respective contacts 22 and 26, as well as bit lines 17 and 37 and word line 19 all running through the cell and into neighboring cells. In particular, programming lines 11 and 13, bit line 17 and word line 19 run into neighboring cell 115 in a first direction, while bit line 37 runs into neighboring cell 215 in a second direction. Word line 19 is in a capacitive relation to a polysilicon plate, forming capacitive device 25. Word line 119 similarly relates to another polysilicon plate (130, shown in FIG. 2) forming capacitive device 125. Each memory cell has an EEPROM memory transistor 23 and a current injector including a fast diode 29, with a cathode connected to an electrical contact 22 and to an electrode of an MOS injector transistor 21. The injector transistor 21 has a single poly control gate (represented by 21A, 21B), described below. MOS injector transistor 21 is biased by either actuation line 36 (21A), or by means of capacitive coupling via word line 19 (21B), or both, depending on the mode of operation. The anode of diode 29 is connected to the transistor substrate and electrical contact 24. Biasing of first program line 11 of transistor 21 provides reverse bias to diode 29. Such reverse bias generates current toward the depth of the substrate. [0018] Program lines 11 and 13 are arranged to provide bias to MOS transistor 21 when appropriate bias is established on actuation line 33 by an n-channel MOS transistor 35 connected as a plate capacitor. EEPROM memory transistor 23 has a distributed floating gate formed by the gates of transistors 35, and 21, essentially lead wire forming line 36, while the control gate is a novel capacitively coupled structure partly formed by word line 19. Continue reading... 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