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12/27/07 - USPTO Class 365 |  41 views | #20070297246 | Prev - Next | About this Page  365 rss/xml feed  monitor keywords

Non-volatile electrically alterable semiconductor memory with control and floating gates and side-wall coupling

USPTO Application #: 20070297246
Title: Non-volatile electrically alterable semiconductor memory with control and floating gates and side-wall coupling
Abstract: In a memory cell array, each memory cell includes a control gate disposed laterally adjacent a floating gate. The memory cells in each memory column are disposed inside a single well. The control gate and the floating gate are disposed between two diffusion regions. Each memory cell may be erased and programmed by applying a combination of voltages to the diffusion regions, the control gate, and the well. (end of abstract)



Agent: Macpherson Kwok Chen & Heid LLP - San Jose, CA, US
Inventors: Andy Yu, Ying W. Go
USPTO Applicaton #: 20070297246 - Class: 365185280 (USPTO)

Non-volatile electrically alterable semiconductor memory with control and floating gates and side-wall coupling description/claims


The Patent Description & Claims data below is from USPTO Patent Application 20070297246, Non-volatile electrically alterable semiconductor memory with control and floating gates and side-wall coupling.

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