| Nitride-based transistors having laterally grown active region and methods of fabricating same -> Monitor Keywords |
|
|
  Nitride-based transistors having laterally grown active region and methods of fabricating sameUSPTO Application #: 20060017064Title: Nitride-based transistors having laterally grown active region and methods of fabricating same Abstract: High electron mobility transistors and/or methods of fabricating high electron mobility transistors that include a first Group III-nitride layer having vertically grown regions, laterally grown regions and a coalescence region are provided. A Group III-nitride channel layer is provided on the first Group III-nitride layer and a Group III-nitride barrier layer is provided on the Group III-nitride channel layer. A drain contact, a source contact and a gate contact are provided on the barrier layer. The gate contact is disposed on a portion of the barrier layer on a laterally grown region of the first Group III-nitride layer and at least a portion of one of the source contact and/or the drain contact is disposed on a portion of the barrier layer on a vertically grown region of the first Group III-nitride layer. (end of abstract) Agent: Myers Bigel Sibley & Sajovec - Raleigh, NC, US Inventors: Adam William Saxler, Scott Sheppard, Richard Peter Smith USPTO Applicaton #: 20060017064 - Class: 257194000 (USPTO) Related Patent Categories: Active Solid-state Devices (e.g., Transistors, Solid-state Diodes), Heterojunction Device, Field Effect Transistor, Doping On Side Of Heterojunction With Lower Carrier Affinity (e.g., High Electron Mobility Transistor (hemt)) The Patent Description & Claims data below is from USPTO Patent Application 20060017064. Brief Patent Description - Full Patent Description - Patent Application Claims
FIELD OF THE INVENTION [0001] The present invention relates to semiconductor devices and, more particularly, to transistors that incorporate nitride-based active layers. BACKGROUND [0002] The present invention relates to transistors formed of semiconductor materials that can make them suitable for high power, high temperature, and/or high frequency applications. Materials such as silicon (Si) and gallium arsenide (GaAs) have found wide application in semiconductor devices for lower power and (in the case of Si) lower frequency applications. These, more familiar, semiconductor materials may not be well suited for higher power and/or high frequency applications, however, because of their relatively small bandgaps (e.g., 1.12 eV for Si and 1.42 for GaAs at room temperature) and/or relatively small breakdown voltages. [0003] In light of the difficulties presented by Si and GaAs, interest in high power, high temperature and/or high frequency applications and devices has turned to wide bandgap semiconductor materials such as silicon carbide (2.996 eV for alpha SiC at room temperature) and the Group III nitrides (e.g., 3.36 eV for GaN at room temperature). These materials, typically, have higher electric field breakdown strengths and higher electron saturation velocities as compared to gallium arsenide and silicon. [0004] A device of particular interest for high power and/or high frequency applications is the High Electron Mobility Transistor (HEMT), which is also known as a modulation doped field effect transistor (MODFET). These devices may offer operational advantages under a number of circumstances because a two-dimensional electron gas (2DEG) is formed at the heterojunction of two semiconductor materials with different bandgap energies, and where the smaller bandgap material has a higher electron affinity. The 2DEG is an accumulation layer in the undoped ("unintentionally doped"), smaller bandgap material and can contain a very high sheet electron concentration in excess of, for example, 10.sup.13 carriers/cm.sup.2. Additionally, electrons that originate in the wider-bandgap semiconductor transfer to the 2DEG, allowing a high electron mobility due to reduced ionized impurity scattering. [0005] This combination of high carrier concentration and high carrier mobility can give the HEMT a very large transconductance and may provide a strong performance advantage over metal-semiconductor field effect transistors (MESFETs) for high-frequency applications. [0006] High electron mobility transistors fabricated in the gallium nitride/aluminum gallium nitride (GaN/AlGaN) material system have the potential to generate large amounts of radio frequency (RF) power because of the combination of material characteristics that includes the aforementioned high breakdown fields, their wide bandgaps, large conduction band offset, and/or high saturated electron drift velocity. A major portion of the electrons in the 2DEG is attributed to polarization in the AlGaN. [0007] HEMTs in the GaN/AlGaN system have already been demonstrated. U.S. Pat. Nos. 5,192,987 and 5,296,395 describe AlGaN/GaN HEMT structures and methods of manufacture. U.S. Pat. No. 6,316,793, to Sheppard et al., which is commonly assigned and is incorporated herein by reference, describes a HEMT device having a semi-insulating silicon carbide substrate, an aluminum nitride buffer layer on the substrate, an insulating gallium nitride layer on the buffer layer, an aluminum gallium nitride barrier layer on the gallium nitride layer, and a passivation layer on the aluminum gallium nitride active structure. SUMMARY OF THE INVENTION [0008] Some embodiments of the present invention provide high electron mobility transistors and/or methods of fabricating high electron mobility transistors that include a first Group III-nitride layer having vertically grown regions, laterally grown regions and a coalescence region. A Group III-nitride channel layer is provided on the first Group III-nitride layer and a Group III-nitride barrier layer is provided on the Group III-nitride channel layer. A drain contact, a source contact and a gate contact are provided on the barrier layer. The gate contact is disposed on a portion of the barrier layer on a laterally grown region of the first Group III-nitride layer and at least a portion of one of the source contact and/or the drain contact is disposed on a portion of the barrier layer on a vertically grown region of the first Group III-nitride layer. [0009] In further embodiments of the present invention, the laterally grown region on which the gate contact is disposed extends toward the drain contact at least as far as a depletion region of a two-dimensional electron gas extends from the gate contact under expected operating conditions. The laterally grown region on which the gate contact is disposed may extend toward the drain contact at least as far as a point where a strength of an electric field is 50% of a strength of an electric field at a drain side edge of the gate contact under expected operating conditions. The laterally grown region on which the gate contact is disposed may extend toward the drain contact at least as far as a point where a strength of an electric field is an order of magnitude less than a strength of an electric field at a drain side edge of the gate contact under expected operating conditions. The laterally grown region on which the gate contact is disposed may extend toward the drain contact at least as far as a point where a strength of an electric field is two orders of magnitude less than a strength of an electric field at a drain side edge of the gate contact under expected operating conditions. [0010] In additional embodiments of the present invention, the laterally grown region on which the gate contact is disposed extends toward the drain contact but not to the drain contact such that the drain contact is disposed on a vertically grown region of the first Group III-nitride layer. Furthermore, the source contact may be disposed on the barrier layer to extend across the coalescence region of the first Group III-nitride layer so as to bridge between two laterally grown regions of the first Group III-nitride layer. The first Group III-nitride layer may be semi-insulating or insulating. [0011] In still further embodiments of the present invention, the laterally grown region on which the gate contact is provided extends from beneath the source contact to beneath the drain contact. In other embodiments of the present invention, the laterally grown region on which the gate contact is provided extends from beneath the gate contact to beneath the drain contact. In additional embodiments, the laterally grown region on which the gate contact is provided may extend from beneath the gate contact toward but not to beneath the drain contact. In some embodiments, the laterally grown region on which the gate contact is provided may extend from beneath the source contact toward but not to beneath the drain contact. In some embodiments of the present invention, the laterally grown region on which the gate contact is provided extends a majority of the distance from source contact to the drain contact. [0012] In some embodiments of the present invention, the laterally grown region on which the gate contact is disposed extends toward the drain contact but not to the drain contact such that the drain contact is disposed on a vertically grown region of the first Group III-nitride layer. In other embodiments, the laterally grown region on which the gate contact is disposed extends to but not beyond the drain contact. In still further embodiments, the laterally grown region on which the gate contact is disposed extends beyond an edge of the drain contact such that at least a portion of the drain contact is disposed on the laterally grown region on which the gate contact is disposed. [0013] In additional embodiments of the present invention, the gate contact is disposed on a first laterally grown region and a second laterally grown region adjacent the first laterally grown region on which the gate contact is disposed extends toward the drain contact but not to the drain contact such that the drain contact is disposed on a vertically grown region of the first Group III-nitride layer. In further embodiments, the gate contact is disposed on a first laterally grown region and a second laterally grown region adjacent the first laterally grown region on which the gate contact is disposed extends to but not beyond the drain contact. In still further embodiments, the gate contact is disposed on a first laterally grown region and a second laterally grown region adjacent the first laterally grown region on which the gate contact is disposed extends beyond an edge of the drain contact such that at least a portion of the drain contact is disposed on the second laterally grown region. [0014] In other embodiments of the present invention, the gate contact is disposed on a first laterally grown region and a second laterally grown region adjacent the first laterally grown region and the second laterally grown region extends toward the drain contact but not to the drain contact such that the drain contact is disposed on a vertically grown region of the first Group III-nitride layer. In further embodiments, the gate contact is disposed on a first laterally grown region and a second laterally grown region adjacent the first laterally grown region and the second laterally grown region extends to but not beyond the drain contact. In some embodiments, the gate contact is disposed on a first laterally grown region and a second laterally grown region adjacent the first laterally grown region and the second laterally grown region extends beyond an edge of the drain contact such that at least a portion of the drain contact is disposed on the second laterally grown region. [0015] In yet further embodiments of the present invention, the gate contact is disposed on a first laterally grown region and a portion of the source contact is disposed on a second laterally grown region adjacent the first laterally grown region. In additional embodiments, the gate contact is disposed on a first laterally grown region and the source contact extends to but not beyond a second laterally grown region adjacent the first laterally grown region. In other embodiments, the gate contact is disposed on a first laterally grown region and the source contact does not extend to a second laterally grown region adjacent the first laterally grown region such that the source contact is disposed on a vertically grown region of the first Group III-nitride layer. [0016] In some embodiments of the present invention, the gate contact is disposed on a first laterally grown region and a second laterally grown region adjacent the first laterally grown region and a portion of the source contact is disposed on the second laterally grown region. In other embodiments, the gate contact is disposed on a first laterally grown region and a second laterally grown region adjacent the first laterally grown region and the source contact extends to but not beyond the second laterally grown region. In still further embodiments, the gate contact is disposed on a first laterally grown region and a second laterally grown region adjacent the first laterally grown region and the source contact does not extend to the second laterally grown region such that the source contact is disposed on a vertically grown region of the first Group III-nitride layer. [0017] In additional embodiments of the present invention, the gate contact is disposed on a first laterally grown region and a second laterally grown region adjacent the first laterally grown region extends from the first laterally grown region toward the drain contact. A portion of the source contact is disposed on the first laterally grown region. In further embodiments, the source contact extends to but not beyond the first laterally grown region. In still further embodiments, the source contact does not extend to the first laterally grown region such that the source contact is disposed on a vertically grown region of the first Group III-nitride layer. [0018] In still further embodiments of the present invention, the transistor further includes a substrate and the first Group III-nitride layer is provided on the substrate. The substrate may include a trench and the laterally grown regions extend over the trench. The substrate may be a silicon carbide substrate and the trench may be aligned perpendicular or parallel to a crystal plane of the silicon carbide substrate. For example, the crystal plane of the silicon carbide substrate may be a plane in the {11{overscore (2)}0} family of planes or the {10{overscore (1)}0} family of planes. A mask layer may be provided in the trench. In other embodiments of the present invention, a mask pattern is provided on the substrate and the laterally grown regions extend over the mask pattern. [0019] In some embodiments of the present invention, the laterally grown regions have substantially vertical growth sidewalls. In other embodiments, the laterally grown regions have trapezoidal growth sidewalls. [0020] In particular embodiments of the present invention, the first Group III-nitride layer includes a gallium nitride layer having deep level impurities therein. [0021] In further embodiments of the present invention, the source contact, the gate contact and the drain contact each include a plurality of contact fingers and the laterally grown regions include a plurality of laterally grown regions separated by vertically grown regions, where a respective gate contact finger is provided on a corresponding one of the plurality of laterally grown regions. Continue reading... Full patent description for Nitride-based transistors having laterally grown active region and methods of fabricating same Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Nitride-based transistors having laterally grown active region and methods of fabricating same patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. Start now! - Receive info on patent apps like Nitride-based transistors having laterally grown active region and methods of fabricating same or other areas of interest. ### Previous Patent Application: Metamorphic buffer on small lattice constant substrates Next Patent Application: Bipolar transistor and fabrication method of the same Industry Class: Active solid-state devices (e.g., transistors, solid-state diodes) ### FreshPatents.com Support Thank you for viewing the Nitride-based transistors having laterally grown active region and methods of fabricating same patent info. IP-related news and info Results in 2.06475 seconds Other interesting Feshpatents.com categories: Computers: Graphics , I/O , Processors , Dyn. Storage , Static Storage , Printers |
||
