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  Network topology for a scalable multiprocessor systemUSPTO Application #: 20060282648Title: Network topology for a scalable multiprocessor system Abstract: A system and method for interconnecting a plurality of processing element nodes within a scalable multiprocessor system is provided. Each processing element node includes at least one processor and memory. A scalable interconnect network includes physical communication links interconnecting the processing element nodes in a cluster. A first set of routers in the scalable interconnect network route messages between the plurality of processing element nodes. One or more metarouters in the scalable interconnect network route messages between the first set of routers so that each one of the routers in a first cluster is connected to all other clusters through one or more metarouters. (end of abstract) Agent: Schwegman, Lundberg, Woessner & Kluth, P.A. - Minneapolis, MN, US Inventors: Martin M. Deneroff, Gregory M. Thorson, Randal S. Passint USPTO Applicaton #: 20060282648 - Class: 712011000 (USPTO) Related Patent Categories: Electrical Computers And Digital Processing Systems: Processing Architectures And Instruction Processing (e.g., Processors), Processing Architecture, Array Processor, Array Processor Element Interconnection The Patent Description & Claims data below is from USPTO Patent Application 20060282648. Brief Patent Description - Full Patent Description - Patent Application Claims
[0001] This application is a continuation of U.S. application Ser. No. 09/408,972, filed on Sep. 29, 1999, which is incorporated herein by reference. FIELD OF THE INVENTION [0002] The present invention relates generally to the field of high-speed digital data processing systems, and more particularly, to interconnection topologies for interconnecting processing element nodes in multiprocessor computer systems. BACKGROUND OF THE INVENTION [0003] Multiprocessor computer systems comprise a number of processing element nodes connected together by an interconnect network. Each processing element node includes at least one processing element. The interconnect network transmits packets of information or messages between processing element nodes. Multiprocessor computer systems having up to hundreds or thousands of processing element nodes are typically referred to as massively parallel processing (MPP) systems. In a typical multiprocessor MPP system, every processing element can directly address all of memory, including the memory of another (remote) processing element, without involving the processor at that processing element. Instead of treating processing element-to-remote-memory communications as an I/O operation, reads or writes to another processing element's memory are accomplished in the same manner as reads or writes to the local memory. In such multiprocessor MPP systems, the infrastructure that supports communications among the various processors greatly affects the performance of the MPP system because of the level of communications required among processors. [0004] Several different topologies have been proposed to interconnect the various processors in such MPP systems, such as rings, stars, meshes, hypercubes, and torus topologies. For example, in a conventional hypercube network, a plurality of microprocessors are arranged in an n-dimensional cube where the number of nodes k in the network is equal to 2.sup.n. In this network, each node is connected to each other node via a plurality of communications paths. The network diameter, the longest communications path from any one node on the network to any other node, is n-links. [0005] Regardless of the topology chosen, one disadvantage of current multiprocessor systems, and in particular MPP systems, is that in order to expand the system, a significant amount of reconfiguration is required. The reconfiguration often involves removing and replacing cables which is very time consuming. Also, as systems increase the number of processors, the number of physical connections required to support the system increases significantly which increases the complexity of the system. [0006] Therefore, it is desired that systems could be easily scaled to increase the number of processors with minimal disruption to the original system configuration. SUMMARY OF THE INVENTION [0007] The present invention provides a system and method for interconnecting a plurality of processing element nodes within a scalable multiprocessor system. Each processing element node includes at least one processor and memory. A scalable interconnect network includes physical communication links interconnecting the processing element nodes in a cluster. A first set of routers in the scalable interconnect network route messages between the plurality of processing element nodes. One or more metarouters in the scalable interconnect network route messages between the first set of routers so that each one of the routers in a first cluster is connected to all other clusters through one or more metarouters. BRIEF DESCRIPTION OF THE DRAWINGS [0008] FIG. 1 is block diagram of a multiprocessor computer system. [0009] FIG. 2 is a block diagram of one embodiment of the interface between a scalable interconnect network and four processing element nodes. [0010] FIG. 3 is a model of a two dimensional (2D) hypercube topology multiprocessor computer system. [0011] FIG. 4 is a model of a three dimensional (3D) hypercube topology multiprocessor computer system. [0012] FIG. 5 illustrates an example embodiment of a logical topology used for multiprocessor computer systems having 129 processors to 160 processors. [0013] FIG. 6 illustrates an example embodiment of a logical topology used for multiprocessor computer systems having 161 processors to 192 processors. [0014] FIG. 7 illustrates an example embodiment of a logical topology used for multiprocessor computer systems having 193 processors to 224 processors. [0015] FIG. 8 illustrates an example embodiment of a logical topology used for multiprocessor computer systems having 225 processors to 256 processors. [0016] FIG. 9 illustrates an example embodiment of a logical topology used for multiprocessor computer systems having up to 288 processors. [0017] FIG. 10 illustrates an example embodiment of a logical topology used for multiprocessor computer systems having up to 320 processors. [0018] FIG. 11 illustrates an example embodiment of a logical topology used for multiprocessor computer systems having up to 352 processors. [0019] FIG. 12 illustrates an example embodiment of a logical topology used for multiprocessor computer systems having up to 384 processors. [0020] FIG. 13 illustrates an example embodiment of a logical topology used for multiprocessor computer systems having up to 416 processors. Continue reading... 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