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Nanoscale latch-array processing enginesNanoscale latch-array processing engines description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20070109014, Nanoscale latch-array processing engines. Brief Patent Description - Full Patent Description - Patent Application Claims
TECHNICAL FIELD [0002] The present invention is related to molecular electronics and, in particular, to nanoscale processing engines with the full computational power of a Turing machine. BACKGROUND OF THE INVENTION [0003] During the past 70 years, enormous progress in the theoretical foundations of computer science, in materials science and integrated circuit fabrication, and in systems design and integration have led to fantastic increases in the computational power, flexibility, and affordability of computers, along with a surprising and equally fantastic decrease in the sizes of, and power consumption and dissipation by, modem computer systems. A currently available, inexpensive desktop personal computer provides far more computing power than a supercomputer of twenty years ago. Much of the progress in computing can be attributed to a steady increase in the density of circuitry that can be manufactured in integrated circuits resulting from a steady decrease in the widths of signal lines and dimensions of submicroscale electronic components that can be fabricated by photolithographic processes. Unfortunately, the tiny dimensions at which signal lines and submicroscale electronic components can be manufactured may be approaching physical limits to further size decreases. Further increases in the density of fabricated submicroscale electronic components may depend on using a very different fabrication strategy, rather than photolithography-based methods. Continued progress in computing may depend either on developing new integrated circuit fabrication methods and materials, or may instead depend on finding entirely new strategies for computing, such as quantum computing, massively parallel computer architectures, or other such innovations. [0004] During the past decade, an entirely new fabrication method for nanoscale electronic circuits and nanoscale electronic components has begun to be developed, and has become a foundation of the emerging field of molecular electronics. One promising type of nanoscale-component fabrication process is based on nanoscale crossbars composed of nanowires, with passive and active electronic components, including resistors, diodes, and various types of transistors, fabricated at selected points of overlap between approximately perpendicular nanowires in stacked, orthogonally oriented layers of parallel nanowires. Working nanowire-crossbar circuits have been fabricated in research laboratories, and have been integrated with conventional submicroscale circuitry to produce tiny, high-density memories and logic circuits. Although nanowire crossbars represent an exciting and promising approach to fabrication of computer components at molecular dimensions, much additional research and development effort is needed for commercial production and integration of nanowire-crossbar-based computer components. Many issues remain concerning the reliability of fabrication of passive and active electronic components at nanowire junctions, and much effort will be needed to efficiently construct dense circuitry at molecular dimensions. Furthermore, it remains a challenge to fabricate fully functional processors using nanowire crossbars, because it is not currently easy to store computed values in nanowire crossbars and to route stored, computed values from one storage location to another within nanowire crossbars. For these reasons, researchers, developers, and manufacturers of submicroscale electronics have recognized the need for simple, universal computing devices, with the full computational power of Turing machines (simple theoretical computing devices used in theoretical studies of computability and undecidability that can solve the class of problems solvable by all currently known computing devices), that can be practically fabricated at molecular dimensions and that can be practically controlled and operated to perform general computation tasks. SUMMARY OF THE INVENTION [0005] One embodiment of the present invention is an array of nanoscale latches interconnected by a nanowire bus to form a latch array. Each nanoscale latch in the nanoscale-latch array serves as a nanoscale register, and is driven by a nanoscale control line. Primitive operations for the latch array can be defined as sequences of one or more inputs to one or more of the nanowire data bus and nanoscale control lines. In various latch-array embodiments of the present invention, information can be transferred from one nanoscale latch to another nanoscale latch in a controlled fashion, and sequences of information-transfer operations can be devised to implement arbitrary Boolean logic operations and operators, including NOT, AND, OR, XOR, NOR, NAND, and other such Boolean logic operators and operations, as well as input and output functions. Nanoscale-latch arrays can be combined and interconnected in an almost limitless number of different ways to construct arbitrarily complex, sequential, parallel, or both parallel and sequential computing engines that represent additional embodiments of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS [0006] FIGS. 1A-C provide different illustrations of a resistive nanowire junction. [0007] FIG. 2 shows the bistable resistivity states of a hysteretic, resistive nanowire junction and resistivity-state transitions under operational control voltages. [0008] FIGS. 3A-B schematically illustrate storage of a single bit of data within a hysteretic, resistive nanoscale junction. [0009] FIG. 4 shows a first embodiment of a nanoscale latch. [0010] FIGS. 5A-E illustrate operation of the first embodiment of the nanoscale latch shown in FIG. 4. [0011] FIGS. 6A-B illustrate transfer of a data value from a first nanoscale latch to a second nanoscale latch on a nanowire data bus, employed in various embodiments of the present invention. [0012] FIGS. 7A-C illustrate operation of a non-inverting nanoscale latch employed in various embodiments of the present invention. [0013] FIGS. 8A-B illustrate transfer of data from a source nanoscale latch to a target nanoscale latch along a nanowire data bus that interconnects non-inverting latches, employed in various embodiments of the present invention. [0014] FIGS. 9A-B illustrate a seven-single-bit-nanoscale latch array used as a register array and representing one embodiment of the present invention. [0015] FIGS. 10A-F illustrate five primitive operations and a Boolean operation, implemented as a sequence of primitive operations, for a single-bit nanoscale register array, such as the single-bit nanoscale register array shown in FIG. 9B, that represents one embodiment of the present invention. [0016] FIG. 11 illustrates an implementation of the program "bit serial adder" for execution on a nanoscale-processing-engine embodiment of the present invention. [0017] FIG. 12 illustrates a possible implementation of a stored-program computer using a single-bit nanoscale-register-array embodiment of the present invention. [0018] FIG. 13 is a schematic diagram of a field-effect-transistor-based nanoscale demultiplexer employed in various embodiments of the present invention. DETAILED DESCRIPTION OF THE INVENTION [0019] The present invention is related to tiny, nanoscale processing engines with the computational power of Turing machines. In one embodiment, a nanoscale processor is fabricated as an array of nanoscale leeches interconnected with one another by a single-bit, nanowire bus, and controlled by a controller and a stored program. The nanoscale latches can be pairwise controlled to implement arbitrary Boolean operations and operators, providing a universal computing machine. In the following discussion, nanoscale latches are first described, followed by a description of nanoscale latch arrays, and finally, a detailed description of the implementation of Boolean operators and operations using primitive operations implemented as sequential application of control signals to nanoscale latches of a nanoscale latch array. An overall architecture for a nanoscale processor is then provided, along with an exemplary program that can be executed by one embodiment of the nanoscale processor of the present invention to add two, arbitrarily long binary numbers. [0020] FIGS. 1A-C provide different illustrations of a resistive nanowire junction. In FIG. 1A, a physical representation of the resistive nanowire junction is provided to represent a picture of a resistive, nanowire junction that might be obtained were optical microscopes of sufficient power available to image nanowire junctions. As shown in FIG. 1A, a first nanowire 102 underlies a second nanowire 104, with the two nanowires 102 and 104 approximately perpendicular to one another. A resistive element 106 lies between the two nanowires, in the region of overlap between the two nanowires. Nanowires may be composed of a few, parallel strands of a conducting polymer, a carbon nanotube, a polymer-like chain of metal or semiconductor atoms or molecules, or other conducting or semiconducting materials that can be fabricated at molecular dimensions. The shapes and cross-sectional geometries of nanowires are determined by the molecules that compose them, but generally are complex at molecular dimensions, rather than the simple rectangular shapes shown in FIG. 1A. The resistive element 106 that lies between the two nanowires at their point of closest contact may be composed of one or a small number of molecules that behave as an electrical resistor. A voltage can be applied across a nanowire junction so that an amount of current flows through the junction that is proportional to the applied voltage and inversely proportional to the resistance of the resistive element 106, according to Ohm's Law. FIG. 1B shows a more schematic illustration of the resistive nanowire junction shown in FIG. 1A. FIG. 1C shows a fully schematic illustration of the resistive nanowire junction shown in FIG. 1A. The schematic convention shown in FIG. 1C is employed throughout the remaining figures to represent resistive nanowire junctions. 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