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  Nand flash memory with densely packed memory gates and fabrication processUSPTO Application #: 20060017085Title: Nand flash memory with densely packed memory gates and fabrication process Abstract: NAND flash memory cell array and fabrication process in which cells having memory gates and charge storage layers are densely packed, with the memory gates in adjacent cells either overlapping or self-aligned with each other. The memory cells are arranged in rows between bit line diffusions and a common source diffusion, with the charge storage layers positioned beneath the memory gates in the cells. The memory gates are either polysilicon or polycide, and the charge storage gates are either a nitride or the combination of nitride and oxide. Programming is done either by hot electron injection from silicon substrate to the charge storage gates to build up a negative charge in the charge storage gates or by hot hole injection from the silicon substrate to the charge storage gates to build up a positive charge in the charge storage gates. Erasure is done by channel tunneling from the charge storage gates to the silicon substrate or vice versa, depending on the programming method. The array is biased so that all of the memory cells can be erased simultaneously, while programming is bit selectable. (end of abstract) Agent: Edward S. Wright - Menlo Park, CA, US Inventors: Prateep Tuntasood, Der-Tsyr Fan, Chiou-Feng Chen USPTO Applicaton #: 20060017085 - Class: 257296000 (USPTO) Related Patent Categories: Active Solid-state Devices (e.g., Transistors, Solid-state Diodes), Field Effect Device, Having Insulated Electrode (e.g., Mosfet, Mos Diode), Insulated Gate Capacitor Or Insulated Gate Transistor Combined With Capacitor (e.g., Dynamic Memory Cell) The Patent Description & Claims data below is from USPTO Patent Application 20060017085. Brief Patent Description - Full Patent Description - Patent Application Claims
BACKGROUND OF THE INVENTION [0001] 1. Field of Invention [0002] This invention pertains generally to semiconductor memory devices and, more particularly, to a NAND flash memory and process of fabricating the same. [0003] 2. Related Art [0004] Nonvolatile memory is currently available in several forms, including electrically programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM), and flash EEPROM. Flash memory has been widely used for high volume data storage in devices such as memory cards, personal digital assistants (PDA's), cellular phones, and MP3 players. Such applications require high density memory, with smaller cell size and reduced cost of manufacture. [0005] The traditional NOR-type stack-gate flash memory cell usually has a bit line contact, a source region, a floating gate, and a control gate, with the control gate being positioned directly above the floating gate. Its relatively large cell size prevents it from being used in very high density data storage applications. [0006] Cell size is smaller in a NAND flash memory array having a series of stack-gate flash memory cells connected in series between a bit-line and a source line, with only one bit-line contact, as illustrated in FIG. 1 and described in greater detail in U.S. Pat. Nos. 4,959,812 and 5,050,125. In this array, a plurality of stack-gate memory cells 21 are connected in series between a bit line diffusion 22 and a source diffusion 23. The cells are formed in a P-well 24 in a substrate 26 of either N- or P-type silicon. Each of the cells has a floating gate 27 fabricated of a conductive material such as polysilicon and a control gate 28 fabricated of a conductive material such as polysilicon or polycide. The control gate is above and in vertical alignment with the floating gate. [0007] Two select gates 29, 30 are included in the array, one near the bit line diffusion 22 and one near source diffusion 23. The bit line 31 for each row is connected to the bit line diffusion by a bit line contact 32 contact. Diffusions 33 are formed in the substrate between the stacked gates and between the stacked gates and the select gates to serve as source and drain regions for the transistors in the memory cells. The bit line diffusions, source diffusion, and diffusions 33 are doped with N-type dopants. [0008] To erase the memory cell, a positive voltage of about 20 volts is applied between the P-well and the control gates, which causes the electrons to tunnel from the floating gates to the channel regions beneath them. The floating gates thus become positively charged, and the threshold voltage of the stack-gate cells becomes negative. [0009] To program the memory cells, the control gates are biased to a level of about 20 volts positive relative to the P-well. As electrons tunnel from the channel region to the floating gates, the floating gates are negatively charged, and the threshold voltage of the stack-gate cells becomes positive. By changing the threshold voltage of a stack-gate cell, the channel beneath it can be in either a non-conduction state (logical) or a conduction state (logical when a zero voltage is applied to the control gate during a read operation. [0010] However, as the fabrication process advances to very smaller geometry, e.g., tens of nanometer, it is difficult to form a high-voltage coupling ratio which is sufficient for program and erase operations while maintaining a small cell size. OBJECTS AND SUMMARY OF THE INVENTION [0011] It is in general an object of the invention to provide a new and improved semiconductor device and process of fabricating the same. [0012] Another object of the invention is to provide a semiconductor device and process of the above character which overcomes the limitations and disadvantages of the prior art. [0013] These and other objects are achieved in accordance with the invention by providing a memory cell array and fabrication process in which memory cells are densly packed in rows between bit line diffusions and a common source diffusion. Each cell has a memory gate and a charge select gate, with the memory gates in adjacent cells being self-aligned with and/or partially overlapping each other. [0014] In some embodiments, programming is done by hot electron injection from the underlying substrate to the charge storage gates to build up a negative charge in the charge storage gates, while in others it is done by hot hole injection from the silicon substrate to the charge storage gates to build up a positive charge in the charge storage gates. Erasure is done by channel tunneling from the charge storage gates to the silicon substrate or vice versa, depending on the programming method. The array is biased so that all of the memory cells in it can be erased simultaneously, while programming is bit selectable. BRIEF DESCRIPTION OF THE DRAWINGS [0015] FIG. 1 is a cross-sectional view of a prior art NAND flash memory array with a series of stack-gate flash memory cells. [0016] FIG. 2 is a cross-sectional view of one embodiment of a NAND flash memory cell array incorporating the invention, taken along line 2-2 in FIG. 4. [0017] FIG. 3 is a cross-sectional view of the embodiment of FIG. 2, taken along line 2-2 in FIG. 4. [0018] FIG. 4 is a top plan view of the embodiment of FIG. 2. [0019] FIGS. 5A-5F are schematic cross-sectional views illustrating the steps in one embodiment of a process for fabricating the memory cell array of FIG. 2 in accordance with the invention. [0020] FIGS. 6 and 7 are circuit diagrams of a small memory arrays as in the embodiment of FIG. 2, showing exemplary bias conditions for erase, program and read operations. [0021] FIGS. 8A-8F, 9A-9F and 10A-10F are schematic cross-sectional views illustrating the steps in additional embodiments of a process for fabricating a NAND flash memory cell array in accordance with the invention. Continue reading... Full patent description for Nand flash memory with densely packed memory gates and fabrication process Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Nand flash memory with densely packed memory gates and fabrication process patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. 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