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09/06/07 - USPTO Class 385 |  91 views | #20070206897 | Prev - Next | About this Page  385 rss/xml feed  monitor keywords

N-nary optical semiconductor transistor and an optical and gate

USPTO Application #: 20070206897
Title: N-nary optical semiconductor transistor and an optical and gate
Abstract: An N-nary photonic transistor (PT) based on a heterojunction optical semiconductor microstructure is presented. The PT has one control signal input, one data signal input, and one output. The lights for each input can be one of the wavelengths within the N number (N-nary) of predetermined lightwaves. The output light of the PT is determined by the inputs in accordance with the switching function of the PT. The PT can be used to construct either N-nary digital logic gates or binary Boolean logic gates. For the N-nary system, both the wavelength domain and intensity domain of the lights are used which forms a two dimensional logic system. An optical AND gate, which can be used as either N-nary or binary, is constructed using the current photonic transistor, which is also presented herein. (end of abstract)



Agent: Shaowen Song Department Of Physics And Computer Science - Waterloo, ON, CA
Inventor: Shaowen Song
USPTO Applicaton #: 20070206897 - Class: 385014000 (USPTO)

Related Patent Categories: Optical Waveguides, Integrated Optical Circuit

N-nary optical semiconductor transistor and an optical and gate description/claims


The Patent Description & Claims data below is from USPTO Patent Application 20070206897, N-nary optical semiconductor transistor and an optical and gate.

Brief Patent Description - Full Patent Description - Patent Application Claims
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[0001] This application is a continuation-in-part of U.S. Provisional Application No. 60/778,394, filed Mar. 3, 2006.

FIELD OF THE INVENTION

[0002] The present invention relates to the field of optical (or photonic) computing, N-nary digital logic, photonic transistor, and optical semiconductor logic gates.

BACKGROUND OF THE INVENTION

[0003] Similar to digital electronics, digital photonic circuits/chips can be built using logic gates, in which light signals, instead of electrical ones, are used to drive the device. When using light, we have two dimensions available for information encoding and computing, which are the light intensity and the wavelength. In other words, we can use N (N.gtoreq.1) number of lightwaves, and each one can be at either zero intensity, to represent the binary 0's, or a pre-selected high intensity, to represent the binary 1's. For computing purposes, we can use either the intensities to represent information or the wavelengths or both. If the intensity is used for information encoding, one can have a multiple binary system with each lightwave having two intensities, one for 0's and the other for 1's. If only one wavelength is used in this case, it becomes a single binary system. On the other hand, if the wavelengths are used to encode information, in this case N.gtoreq.2, we can have an N-valued system with each lightwave being at a constant intensity to be one of the values in the N-valued digital system. If two wavelengths are used in this case, it also becomes a binary system, with one wavelength representing the 0's and the other representing the 1's. However, if both the intensities and the wavelengths are used for information representation and manipulation, we can have a two dimensional logic system that not only provides high computation capacity but also can be constructed in a way so that the transitional functions among the digital values in the system to be simple and implantable by optical semiconductors. Based on these considerations, we constructed an N-valued digital logic system that defines the transition functions among the N values to achieve N-nary computing using both light intensities (only two intensities are used) and wavelengths (N number of wavelengths with N.gtoreq.1). An N-nary Digital Photonic (NDP) system is established by implementing the transition functions through N-nary phonic logic gates. Using the photonic logic gates one can construct N-nary digital logic photonic circuits/devices. This system was disclosed in U.S. Pat. No. 6,778,303. An N-nary Optical Random Access Memories (O-RAM), according to the N-valued digital logic, was disclosed in U.S. Pat. No. 6,647,163. The design processes of any digital optical devices using the logic gates are similar to those of the binary Boolean digital system. But, the logic used is the N-valued digital logic instead of the Boolean binary logic.

[0004] One approach of implementing the N-nary photonic logic gates is to first design the photonic transistor (following the same naming convention of digital electronics), which is a micro-device that allows one lightwave to switch on or off another lightwave. The transistors are then used to construct the photonic gates.

[0005] It is worth noting that N-valued logic is not unique. One can construct different logic systems for different applications (Refer to Rescher, N., Many-valued Logic, McGraw-Hill 1969). The larger the N is chosen, the larger the number of logic systems that can be devised. When a logic system is designed for computing purposes, it requires that the logic have two fundamental properties: completeness and implementability. The completeness means that the logic defines all necessary operators (transition functions) to achieve information storage and data computations, and the implementability means that the logic is implementable by some kind of physical media, in order to be useful. The NDP system disclosed in U.S. Pat. No. 6,778,303 was developed to satisfy both these conditions. The key elements of implementing the NDP are logic gates which in turn can be constructed by the herein disclosed N-nary photonic transistor.

[0006] This present invention is an N-nary photonic transistor (PT) based on a heterojunction optical semiconductor microstructure. The photonic transistor design and computer simulation results are presented. The photonic transistor design presented here has the features of being small in size and power consumption, which makes it useful for integrated photonic chips. An example of using the photonic transistor to construct an optical AND (O-AND) gate (Refer to U.S. Pat. No. 6,778,303) is also presented.

SUMMARY OF THE INVENTION

[0007] An N-nary photonic transistor (PT) based on a heterojunction optical semiconductor microstructure is herein disclosed. The PT has one control signal input, one data signal input, and one output. The lights for each input can be one of the wavelengths within the N number (N-nary) of predetermined lightwaves. A special case, when one wavelength is used for both inputs, the current PT becomes a binary transistor. The PT can be used to construct either N-nary digital logic gates or binary Boolean logic gates. For the N-nary system, both the wavelength domain and intensity domain of the lights are used which forms a two dimensional logic system. An optical AND gate, which can be used as either N-nary or binary, is constructed using the current photonic transistor. Computer simulations using commercial software produced satisfactory results for both the photonic transistor and the optical NAD gate.

BRIEF DESCRIPTION OF THE DRAWINGS

[0008] FIG. 1. The configuration of the photonic transistor

[0009] FIG. 2. The logic symbol of the photonic transistor

[0010] FIG. 3. The cross-section of the photonic transistor

[0011] FIG. 4. Control input signal (.lamda.=1560 nm) for simulation case-1

[0012] FIG. 5. Data input signal (.lamda.=1550 nm) for simulation case-1

[0013] FIG. 6. The output signal of the photonic transistor (.lamda.=1550 nm) of simulation case-1

[0014] FIG. 7. Control input signal with wavelength of 1540 nm for simulation case-2

[0015] FIG. 8. The output signal of the photonic transistor (.lamda.=1550 nm) for simulation case-2

[0016] FIG. 9 The O-AND gate construction using the herein disclosed photonic transistor

[0017] FIG. 11. The logic operator for the O-AND gate

[0018] FIG. 10. The logic symbol of the O-AND gate

[0019] FIG. 12. The signal input of the O-AND gate simulation case-1

[0020] FIG. 13. The control input of the O-AND gate simulation case-1

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