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  Multiple layer and crystal plane orientation semiconductor substrateUSPTO Application #: 20080102566Title: Multiple layer and crystal plane orientation semiconductor substrate Abstract: A semiconductor on insulator substrate and a method of fabricating the substrate. The substrate including: a first crystalline semiconductor layer and a second crystalline semiconductor layer; and an insulating layer bonding a bottom surface of the first crystalline semiconductor layer to a top surface of the second crystalline semiconductor layer, a first crystal direction of the first crystalline semiconductor layer aligned relative to a second crystal direction of the second crystalline semiconductor layer, the first crystal direction different from the second crystal direction. (end of abstract) Agent: Schmeiser, Olsen & Watts - Latham, NY, US Inventors: Toshiharu Furukawa, David V. Horak, Charles W. Koburger, Leathen Shi USPTO Applicaton #: 20080102566 - Class: 438150000 (USPTO) Related Patent Categories: Semiconductor Device Manufacturing: Process, Making Field Effect Device Having Pair Of Active Regions Separated By Gate Structure By Formation Or Alteration Of Semiconductive Active Regions, On Insulating Substrate Or Layer (e.g., Tft, Etc.), Specified Crystallographic Orientation The Patent Description & Claims data below is from USPTO Patent Application 20080102566. Brief Patent Description - Full Patent Description - Patent Application Claims
[0001] This application is a Division of and claims priority of copending U.S. patent application Ser. No. 10/906,557 filed on Feb. 24, 2005. FIELD OF THE INVENTION [0002] The present invention relates to the field of semiconductor substrates; more specifically, it relates a method of fabricating a semiconductor substrate having multiple crystalline layers with different crystal plane orientations. BACKGROUND OF THE INVENTION [0003] In advanced semiconductor devices, individual devices such as transistors are positioned on semiconductor substrates relative to the crystal orientation of the substrate in order to take advantage of the fact that certain device parameters change based on the alignment of device structures relative to the crystal planes of the substrate. However, this often leads to integrated circuit chip edges that are no longer aligned to preferred crystal cleavage planes of the substrate, making dicing of the substrate into individual integrated circuit chips difficult and often resulting in wafer breakage. What is needed is a semiconductor substrate and a method of fabricating the substrate that allows device structures that take advantage of particular crystal plane alignments that at the same time can be easily diced into individual integrated circuit chips. SUMMARY OF THE INVENTION [0004] A semiconductor substrate of the present invention comprises an insulating layer between an upper semiconductor layer and a lower semiconductor layer. A first crystal direction in the upper layer is rotationally displaced from a second crystal direction in the lower semiconductor layer. The edges of integrated circuit chips formed in the upper semiconductor layer are aligned to the second crystal direction to enhance dicing while some or all of devices formed in the integrated circuit chips have structures aligned to the first crystal direction. [0005] A first aspect of the present invention is a substrate, comprising: a first crystalline semiconductor layer and a second crystalline semiconductor layer; and an insulating layer bonding a bottom surface of the first crystalline semiconductor layer to a top surface of the second crystalline semiconductor layer, a first crystal direction of the first crystalline semiconductor layer aligned relative to a second crystal direction of the second crystalline semiconductor layer, the first crystal direction different from the second crystal direction. [0006] A second aspect of the present invention is a method of fabricating a substrate, comprising: providing a first crystalline semiconductor substrate, providing a second crystalline semiconductor substrate; aligning a first crystal direction of the first crystalline semiconductor substrate to a second crystal direction of the second crystalline semiconductor substrate, the first crystal direction different from the second crystal direction; and forming an insulating layer between a bottom surface of the first crystalline semiconductor substrate and a top surface of the second crystalline semiconductor substrate, the insulating layer bonding the first crystalline semiconductor substrate to the second crystalline semiconductor substrate, [0007] A third aspect of the present invention is an integrated circuit chip, comprising: a first crystalline semiconductor layer and a second crystalline semiconductor layer; an insulating layer bonding a bottom surface of the first crystalline semiconductor layer to a top surface of the second crystalline semiconductor layer, a first crystal direction of the first crystalline semiconductor layer aligned relative to a second crystal direction of the second crystalline semiconductor layer, the first crystal direction different from the second crystal direction; a field effect transistor comprising a source region, a drain region and a channel region separating the source and drain regions, the source, drain and a channel regions formed in the first crystalline semiconductor layer, a lengthwise direction of the channel extending between the source and drain regions aligned with both the first and the second directions; and at least one edge of the integrated circuit chip aligned with the second direction. [0008] A fourth aspect of the present invention is a method of fabricating an integrated circuit chip, comprising: providing a semiconductor-on-insulator substrate comprising a first crystalline semiconductor layer and a second crystalline semiconductor layer, a first crystal direction of the first crystalline semiconductor substrate aligned relative to a second crystal direction of the second crystalline semiconductor substrate, the first crystal direction different from the second crystal direction, an insulating layer formed between a bottom surface of the first crystalline semiconductor substrate and a top surface of the second crystalline semiconductor substrate, the insulating layer bonding the first crystalline semiconductor substrate to the second crystalline semiconductor; forming a field effect transistor comprising a source region, a drain region and a channel region separating the source and drain regions, the source, drain and a channel regions formed in the first crystalline semiconductor layer, a lengthwise direction of the channel extending between the source and drain regions aligned with both the first and the second directions; and dicing the semiconductor-on-insulator substrate along the second direction to form at least one edge of the integrated circuit chip. BRIEF DESCRIPTION OF DRAWINGS [0009] The features of the invention are set forth in the appended claims. The invention itself, however, will be best understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein: [0010] FIG. 1 is a top view of an exemplary {100} surfaced semiconductor substrate; [0011] FIG. 2 illustrates an exemplary semiconductor substrate according to the present invention; [0012] FIGS. 3A through 3E are side views of the fabrication of an exemplary semiconductor substrate according to the present invention; [0013] FIG. 4 is a top view illustrating alignment of integrated circuit chips on the semiconductor substrate of FIG. 2; and [0014] FIG. 5 is a top view illustrating alignment of a first type of device to an integrated circuit chip fabricated on a semiconductor substrate according to the present invention; and DETAILED DESCRIPTION OF THE INVENTION [0015] For the purposes of the present invention, the term wafer should be considered as and exemplary version of the more general term substrate. [0016] In crystalline solids, the atoms which make up the solid are spatially arranged in a periodic fashion called a lattice. A crystal lattice contains a volume, which is representative of the entire lattice and is regularly repeated throughout the crystal. In describing crystalline semiconductor materials in the present disclosure, the following conventions will be used: [0017] The directions in a lattice are expressed as a set of three integers with the same relationship as the components of a vector in that direction. For example, in cubic lattices, such as silicon, that has a diamond crystal lattice, a body diagonal exists along the [111] direction with the [ ] brackets denoting a specific direction. Many directions in a crystal lattice are equivalent by a symmetry transformation, depending upon the arbitrary choice of orientation axes. For example, crystal directions in the cubic lattice [100], [010] and [001] are all crystallographically equivalent. A direction and all its equivalent directions are denoted by < > brackets. Thus, the designation of the <100> direction includes the equivalent [100], [010] and [001] positive directions as well as the equivalent negative directions [-100], [0-10] and [00-1]. [0018] Planes in a crystal may also be identified with a set of three integers. They are used to define a set of parallel planes and each set of integers enclosed in ( ) parentheses identifies a specific plane. For example the proper designation for a crystal plane perpendicular to the [100] direction is (100). Thus, if either a direction or a plane of a cubic lattice is known, its perpendicular counterpart may be quickly determined without calculation. Many planes in a crystal lattice are equivalent by a symmetry transformation, depending upon the arbitrary choice of orientation axes. For example, the (100), (010) and (001) planes are all crystallographically equivalent. A plane and all its equivalent planes are denoted by { } parentheses. Thus, the designation of the {100} plane includes the equivalent (100), (010) and (001) positive planes as well as the equivalent planes (-100), (0-10) and (00-1). [0019] FIG. 1 is a top view of an exemplary {100} surfaced semiconductor substrate. In FIG. 1, a [100] direction of a {100} silicon substrate 100 is seen to be rotated 45.degree. from a Continue reading... Full patent description for Multiple layer and crystal plane orientation semiconductor substrate Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Multiple layer and crystal plane orientation semiconductor substrate patent application. Patent Applications in related categories: ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. 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