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  Multiple execution-path systemUSPTO Application #: 20080098257Title: Multiple execution-path system Abstract: A multiple execution-path flash system includes a main flash image with primary and secondary POST and Boot executable files. The secondary executables are offset from the primary executables by a predetermined offset address. If corrupted data is encountered during Boot, the exception handler sets an offset bit resulting in the predetermined offset address being added to the current instruction address. If corrupted data is encountered in the secondary executables, the offset bit is reset. An optional redundant flash image may also be used. A failure at the same relative address in the primary and secondary executables of the main flash image will cause the exception handler to transfer control to the redundant flash image. A subsequent failure at the same relative address in the primary and secondary executables of the redundant flash image will cause the redundant exception handler to transfer control back to the main flash image. (end of abstract)
Agent: Quarles & Brady LLP - Tucson, AZ, US Inventors: Stephen L. Blinick, Charles S. Cardinell, Ricardo S. Padilla USPTO Applicaton #: 20080098257 - Class: 714005000 (USPTO) Related Patent Categories: Error Detection/correction And Fault Detection/recovery, Data Processing System Error Or Fault Handling, Reliability And Availability, Fault Recovery, By Masking Or Reconfiguration, Of Memory Or Peripheral Subsystem The Patent Description & Claims data below is from USPTO Patent Application 20080098257. Brief Patent Description - Full Patent Description - Patent Application Claims
CROSS-REFERENCE TO RELATED APPLICATIONS [0001] This application a continuation of U.S. patent application Ser. No. 11/031,605 filed Jan. 7, 2005, the disclosure of which is hereby incorporated by reference as if set forth in its entirety herein. BACKGROUND OF THE INVENTION [0002] 1. Field of the Invention [0003] This invention is related in general to the field of bootable input/output adapters. In particular, the invention consists of a device for providing multiple alternate boot paths. [0004] 2. Description of the Prior Art [0005] In a digital processing system, input/output cards referred to as adapters are often used to communicate with devices external to the digital processing system. These adapters traditionally communicate with a central processor of the digital processing system or with each other through a data bus or network. An adapter may be an embedded system, i.e., may include a processing device that must be initialized during power-on and activation. During power-on self-test ("POST"), an adapter's hardware is exercised and diagnostics are performed. During Bootup, an adapter with an embedded processor will initialize the processor and other hardware external to the processor such as memory, and will perform an initial microcode load ("IML"). [0006] Executable programs are stored on the adapter and loaded into the processor during the Boot process. These executables may include a POST executable for performing the power-on self-test, a Kernel or Boot executable responsible for directing the Bootup, and an Exception Handler executable for identifying errors during the Boot process and taking corrective action. [0007] These executable programs are usually maintained in a memory device on the adapter. A common memory device used for this purpose is a Flash memory. The Flash memory is a non-volatile memory device that maintains its data, even when its power source has been turned off or disconnected. A traditional embedded system, such as an adapter, will include a flash image that includes the Kernel, POST, and exception handling executables. A system with a single-path flash includes a single flash image with only one Kernel executable, one POST executable, and one exception handling executable. [0008] A problem may occur if one or more memory locations within the Flash device contain erroneous information. This may occur if the one or more memory locations are defective, an external occurrence has caused the data in the memory locations to become corrupted, or if the process of programming the flash device was interrupted or aborted. Encountering a flash image problem in a single-path flash system requires that the flash be reprogrammed, that the flash device be replaced, or that the adapter possessing the flash device be replaced. [0009] One potential solution is to utilize a redundant flash image including a copy of the Kernel, POST, and exception handler executables. If corrupt information is encountered during the POST of Boot process of the primary flash image, the primary exception handling executable will switch control to the redundant flash image. If the redundant flash image is viable, the POST and Boot processes are loaded into the processor and executed. Alternatively, the Boot and POST processes of the embedded system may be monitored by an external device, such as another adapter or embedded system. If the primary exception handling executable generates an error message, the external device may swap the redundant flash image for the primary flash image and reset the adapter. However, the process of swapping image files and resetting the adapter may take a significant amount of time. Additionally, if the redundant flash image is also corrupted, the adapter will fail to execute its POST and Boot executables requiring that the flash images be programmed, the flash devices be replaced, or the adapter be replaced. Accordingly, it would be advantageous to have a system for providing an alternate boot path that does not require swapping a primary flash image with a redundant flash image. Additionally, it is desirable to have a system for booting from flash images, even if all the flash images include areas of corrupted information. SUMMARY OF THE INVENTION [0010] The invention disclosed herein utilizes a multiple execution-path flash system to allow for successful loading of executable files. A main flash image includes a primary POST executable, a primary Boot executable, and an exception handling executable. Additionally, the main flash image includes a secondary POST executable and a secondary Boot executable, both of which are offset from their corresponding primary executables by a predetermined offset address. If an error condition occurs when loading either the primary POST executable or the primary Boot executable, the exception handling executable will set an offset bit. If the offset bit has been set, a predetermined offset address will be added to the current instruction address being loaded by the processor, resulting in instructions being loaded into the process from a secondary executable. [0011] If another error condition occurs during the execution of the secondary executables, the exception handling executable will reset the offset bit. The current instruction address will not be offset by the predetermined offset address and control will return to the primary executables. In this manner, multiple data corruptions may be encountered without interrupting the POST and Boot processes. [0012] If both the primary executables and the secondary executables contain corrupt information at the same relative locations, the exception handler cannot overcome an execution problem by setting or resetting the offset bit. Rather, the exception handler must turn control over to a redundant flash image. Alternatively, an external process may recognize an error code generated by the exception handler, swap the redundant flash image with the primary flash image, and reset the adapter. If the redundant flash image also includes a multiple-path execution path, corrupted data within the redundant flash image may be bypassed as in the primary flash image. [0013] Yet another advantage of the invention is realized if corrupted data is encountered at the same relative addresses of the primary and secondary executables within the redundant flash image. If this occurs, the exception handling executable within the redundant flash image can turn control back over to the main flash image. Alternatively, an external process may recognize the error code generated by the redundant exception handler and swap the redundant flash image with the main flash image again, returning control to the main flash image after resetting the adapter. [0014] If control is transferable between the main and redundant flash images without resetting the adapter, the POST and Boot processes will complete unless corrupted information is encountered at the same relative memory locations within the primary and second executables of both the main and redundant flash images. If the adapter must be reset after transferring control between the main and redundant flash images, then the POST and Boot processes will complete unless corrupted information is encountered at first relative memory locations within the primary and secondary executables of the main flash image and corrupted information is encountered at second relative memory locations within the primary and secondary executables of the redundant flash image. [0015] Various other purposes and advantages of the invention will become clear from its description in the specification that follows and from the novel features particularly pointed out in the appended claims. Therefore, to the accomplishment of the objectives described above, this invention comprises the features hereinafter illustrated in the drawings, fully described in the detailed description of the preferred embodiments and particularly pointed out in the claims. However, such drawings and description disclose just a few of the various ways in which the invention may be practiced. BRIEF DESCRIPTION OF THE DRAWINGS [0016] FIG. 1 is a block diagram illustrating a multiple execution-path flash system including a processor and a main memory device. [0017] FIG. 2a is a block diagram illustrating a first embodiment of the processor of FIG. 1. [0018] FIG. 2b is a block diagram illustrating a second embodiment of the processor of FIG. 1. [0019] FIG. 3a is a flow chart illustrating a multiple execution-path algorithm utilizing primary and secondary executables according to the invention. [0020] FIG. 3b is a flow chart illustrating the algorithm of FIG. 3a with the added step of returning control back to the primary executables. Continue reading... Full patent description for Multiple execution-path system Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Multiple execution-path system patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. 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