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Multiple channel modules and bus systems using sameMultiple channel modules and bus systems using same description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20070120575, Multiple channel modules and bus systems using same. Brief Patent Description - Full Patent Description - Patent Application Claims
CROSS-REFERENCE TO RELATED APPLICATIONS [0001] This patent application is a divisional of U.S. patent application Ser. No. 11/054,955, filed Feb. 11, 2005, which is a continuation of U.S. patent application Ser. No. 10/695,854, filed Oct. 30, 2003, now U.S. Pat. No. 6,898,085, issued May 24, 2005, which is a divisional of U.S. patent application Ser. No. 09/839,642, filed Apr. 20, 2001, now U.S. Pat. No. 6,765,800, issued Jul. 20, 2004, which is a continuation-in-part of U.S. patent application Ser. No. 09/568,424, filed May 10, 2000, now U.S. Pat. No. 6,545,875, issued Apr. 8, 2003, each of which is hereby incorporated by reference herein in its entirety. FIELD OF THE DISCLOSURE [0002] The present disclosure is directed to bus systems. More particularly, the present disclosure is directed to a bus system including one or more modules implementing one or more communications channel(s). BACKGROUND OF THE DISCLOSURE [0003] Conventional bus systems are typically implemented in single channel architectures. While conventional bus systems have been implemented using modules, the modules in such systems have merely been arranged in a serial relationship on a motherboard. For example, consider the bus system shown in FIG. 1. This bus system is characterized by a master 11 mounted on a motherboard 10. A number of connectors 13 are also mounted on motherboard 10. Each connector 13 is adapted to receive a module 14 comprising one or more integrated circuits 15. Thus, by means of a connector 13, a module 14 is mechanically mounted and electrically connected within the bus system. [0004] One or more bus(es) 16 forms the communications channel between master 11 and a termination resistor 12. Bus 16 typically comprises a number of signals lines communicating control information, address information, and/or data. The signal lines forming bus 16 traverse the motherboard and/or the modules to electrically connect the integrated circuits 15 to master 11. [0005] There are numerous problems associated with such conventional bus systems. For example, the serial arrangement of the connectors and associated modules creates a relatively lengthy communications channel. Since there are many factors limiting the maximum practical length of a communications channel, channel length should, wherever reasonably possible, be minimized. [0006] Conventional bus systems are also characterized by numerous electrical connection points between the connectors and the bus portions traversing the motherboard, between the modules and the connectors, and between the integrated circuits and the bus portion traversing the modules. Improperly matched electrical connections often produce impedance discontinuities which tend to degrade signal transmission characteristics on the bus. Accordingly, the number of impedance discontinuities associated with the bus connections should be minimized. [0007] Such conventional bus systems present a very static architecture which may not lend itself to the efficient utilization of available space within a larger system. For example, a maximum, pre-set number of connectors is typically provided within the conventional bus system, regardless of the actual number of modules initially contemplated for the bus system. Upgrading the bus system to include additional modules requires that a sufficient number of connectors be provided up to the maximum length (or capacity) of the channel. Typically, empty connectors are filled with dummy modules until they are needed. Absent these spare connectors, upgrading the bus system to include an additional module would require that the motherboard be replaced. [0008] Finally, the static architecture of the conventional bus system provides a "one size fits all" approach to larger systems incorporating the bus system. The serial arrangement of connectors and modules on a motherboard may produce an undesirably large footprint within the larger system. Further, this configuration does not lend itself to irregular or crowded spaces within the larger system. SUMMARY OF THE DISCLOSURE [0009] The present disclosure provides, in certain embodiments, modules and bus system architectures which reduce channel length and/or minimize bus connection discontinuities. Bus system architectures provided by the present disclosure may be flexibly configured according to an end user's requirements. Numerous possibilities exist for customized bus system configurations using the modules and interconnection schemes provided by the present disclosure. Multiple channels may be implemented on a single module and multiple modules may be connected to provide bus systems having relative small vertical profiles and/or horizontal footprints. The modules and/or bus system architectures may utilize various types of connectors, including for example finger connectors, edge connectors, and edge fingers. Any other element capable of providing an electrical connection (e.g., contacts, pins, leads, wire bonds, solder balls, etc.) may be substituted for the connectors of the modules, bus systems architectures and memory systems of the present disclosure. Also, a single connector may be substituted for a plurality of connectors. From the perspective of a module, a connector may allow signals to enter the module from elsewhere and/or may allow signals to exit the module. Certain connectors are referred to herein as "ingress" or "input" connectors while certain others are referred to herein as "egress" or "output" connectors. It is understood that input connectors, ingress connectors, output connectors and egress connectors may allow signals to travel in a first direction, a second direction or bidirectionally. In preferred embodiments however, a data signal sent from a memory controller to a memory device on a module will pass onto the module through an "input" or "ingress" connector and off of the module through an "output" or "egress" connector. Such data signal may be sampled by the memory device after passing onto the module. [0010] In one aspect, the present disclosure provides a module formed from a printed circuit board (PCB) having primary first and second surfaces and having first and second ends, a plurality of integrated circuits (ICs) populating at least one of the first and second surfaces, a first set of edge fingers disposed at the first end and on the first surface of the PCB, a second set of edge fingers disposed at the first end and on the second surface of the PCB, a folded bus extending from the first set of edge fingers, substantially traversing the length of the first surface, folding back at the second end, substantially traversing the length of the second surface and terminating at the second set of edge fingers, and a right-angle connector mounted on either the first or second surface at the first end, and adapted to mechanically receive and electrically connect another module. [0011] In another aspect, the present disclosure provides a module adapted for use in a bus system and including; a printed circuit board (PCB) having primary first and second surfaces, and having first and second ends, a plurality of integrated circuits (ICs) populating at least one of the first and second surfaces, a set of edge fingers disposed at the first end of the PCB and on either the top or bottom surface of the PCB, a right-angle connector adapted to mechanically receive and electrically connect another module, the right-angle connector being mounted on either the bottom or top surface of the PCB opposite the surface on which the set of edge fingers are disposed and at the second end of the PCB, and a bus extending from the set of edge fingers, substantially traversing the length of the module, and terminating at the right-angle connector. [0012] In yet another aspect, the present disclosure provides a module adapted to be connected within a plurality of bus system modules, the module including a printed circuit board (PCB) having first and second primary surfaces, first and second primary edges, and first and second ends, a plurality of integrated circuits (ICs) populating at least one of the primary first and second surfaces, a first set of edge fingers disposed on the first primary edge between first and second ends and on the first surface of the PCB, a second set of edge fingers disposed on the first primary edge between first and second ends and on the second surface of the PCB, wherein the first and second set of edge fingers are adapted to connect with an electrical connector associated with another module or a motherboard, a bus comprising a plurality of signal lines running from at least one of the first and second set of edge fingers to a flex tape connector connected at the second primary edge of the PCB between the first and second ends, and an electrical connector connected to the flex tape. [0013] In still another aspect, the present disclosure provides a motherboard and a plurality of modules arranged from a first module to a last module, wherein the motherboard comprises a controller and a right-angle connector adapted to mechanically receive and electrically connect the first module, and wherein each one of the plurality of modules comprises a right-angle connector adapted to receive another one of the plurality of modules, such that, once connected via respective right-angle connectors, the motherboard and the plurality of modules are disposed in parallel one to another. [0014] In a further aspect, the present disclosure provides a module formed from a printed circuit board (PCB) having first and second primary surfaces and having a first end, a plurality of integrated circuits (ICs) populating at least one of the first and second primary surfaces, a first and second set of input finger connectors disposed on at least one of the first and second primary surfaces proximate to the first end, a first and second set of output finger connectors disposed on at least one of the first and second primary surfaces proximate to the first end, and a bus having a first channel extending from the first set of input finger connectors to the first set of output finger connectors and having a second channel extending from the second set of input finger connectors to the second set of output finger connectors, the bus connected to the plurality of ICs. In a preferred embodiment, the first and second set of input finger connectors and the first and second set of output finger connectors are disposed on at least one of the first and second primary surfaces at the first end. [0015] In yet another aspect, the present disclosure provides a module including a first printed circuit board (PCB) having first and second primary surfaces and having a first and second ends, one or more integrated circuits (ICs) populating at least one of the first and second primary surfaces, a set of finger connectors disposed proximate to the first end of the first PCB and on either the first or second primary surface of the first PCB, a conductive interconnect electrically connected to the first PCB proximate to the second end of the first PCB, and a bus extending from the set of finger connectors, substantially traversing the first PCB between the first and second ends and traversing the conductive interconnect. The conductive interconnect is adapted to receive a second PCB populated with one or more ICs. In one preferred embodiment, the module further comprises a connector connecting the conductive interconnect to the first PCB. In another preferred embodiment, the module further comprises a spacer disposed between the first and second PCB's. In yet another preferred embodiment, the set of finger connectors are disposed at the first end of the first PCB, the spacer is attached to the first PCB at the second end of the first PCB, and the conductive interconnect electrically connects the connector to the first PCB at the second end of the first PCB. BRIEF DESCRIPTION OF THE DRAWINGS [0016] FIG. 1 illustrates a conventional bus system architecture; [0017] FIG. 2 illustrates a module adapted for use within the present disclosure; [0018] FIG. 3A is an edge view of one embodiment of a module according to the present disclosure; [0019] FIGS. 3B and 3C are respectively top and bottom views of a single channel module according to the embodiment shown in FIG. 3A; Continue reading about Multiple channel modules and bus systems using same... Full patent description for Multiple channel modules and bus systems using same Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Multiple channel modules and bus systems using same patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. 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