| Multi-queue fifo memory systems that utilize read chip select and device identification codes to control one-at-a-time bus access between selected fifo memory chips -> Monitor Keywords |
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Multi-queue fifo memory systems that utilize read chip select and device identification codes to control one-at-a-time bus access between selected fifo memory chipsRelated Patent Categories: Electrical Computers And Digital Processing Systems: Memory, Storage Accessing And Control, Control TechniqueMulti-queue fifo memory systems that utilize read chip select and device identification codes to control one-at-a-time bus access between selected fifo memory chips description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20060155940, Multi-queue fifo memory systems that utilize read chip select and device identification codes to control one-at-a-time bus access between selected fifo memory chips. Brief Patent Description - Full Patent Description - Patent Application Claims
REFERENCE TO PRIORITY APPLICATION [0001] This application claims priority to U.S. Provisional Application Ser. No. 60/642,776, filed Jan. 10, 2005, the disclosure of which is hereby incorporated herein by reference. CROSS-REFERENCE TO RELATED APPLICATION [0002] This application is related to commonly assigned U.S. application Ser. No. 10/721,974, filed Nov. 24, 2003, the disclosure of which is hereby incorporated herein by reference. FIELD OF THE INVENTION [0003] The present invention relates to integrated circuit memory devices and methods of operating same, and more particularly to buffer memory devices and methods of operating buffer memory devices. BACKGROUND OF THE INVENTION [0004] Semiconductor memory devices can typically be classified on the basis of memory functionality, data access patterns and the nature of the data storage mechanism. For example, distinctions are typically made between read-only memory (ROM) devices and read-write memory (RWM) devices. The RWM devices typically have the advantage of offering both read and write functionality with comparable data access times. Typically, in RWM devices, data is stored either in flip-flops for "static" memory devices or as preset levels of charge on a capacitor in "dynamic" memory devices. As will be understood by those skilled in the art, static memory devices retain their data as long as a supply of power is maintained, however, dynamic memory devices require periodic data refreshing to compensate for potential charge leakage. Because RWM devices use active circuitry to store data, they belong to a class of memory devices known as "volatile" memory devices because data stored therein will be lost upon termination of the power supply. ROM devices, on the other hand, may encode data into circuit topology (e.g., by blowing fuses, removing diodes, etc.). Since this latter type of data storage may be hardwired, the data cannot be modified, but can only be read. ROM devices typically belong to a class of memory devices known as "nonvolatile" memory devices because data stored therein will typically not be lost upon termination of the power supply. Other types of memory devices that have been more recently developed are typically referred to as nonvolatile read-write (NVRWM) memory devices. These types of memory devices include EPROM (erasable programmable read-only memory), E.sup.2PROM (electrically erasable programmable read-only memory), and flash memories, for example. [0005] An additional memory classification is typically based on the order in which data can be accessed. Here, most memory devices belong to the random-access class, which means that memory locations can be read from or written to in random order, typically by supplying a read or write address. Notwithstanding the fact that most memory devices provide random-access, typically only random-access RWM memories use the acronym RAM. Alternatively, memory devices may restrict the order of data access to achieve shorter data access times, reduce layout area and/or provide specialized functionality. Examples of such specialized memory devices include buffer memory devices such as first-in first-out (FIFO) memory devices, last-in first-out (LIFO or "stack") memory devices, shift registers and content addressable memory (CAM) devices. [0006] A final classification of semiconductor memories is based on the number of input and output ports associated with the memory cells therein. For example, although most memory devices have unit cells therein that provide only a single port which is shared to provide an input and output path for the transfer of data, memory devices with higher bandwidth requirements often have cells therein with multiple input and output ports. However, the addition of ports to individual memory cells typically increases the complexity and layout area requirements for these higher bandwidth memory devices. [0007] Single-port memory devices are typically made using static RAM cells if fast data access times are requiring, and dynamic RAM cells if low cost is a primary requirement. Many FIFO memory devices use dual-port RAM-based designs with self-incrementing internal read and write pointers to achieve fast fall-through capability. As will be understood by those skilled in the art, fall-through capability is typically measured as the time elapsing between the end of a write cycle into a previously empty FIFO and the time an operation to read that data may begin. Exemplary FIFO memory devices are more fully described and illustrated at section 2.2.7 of a textbook by A. K. Sharma entitled "Semiconductor Memories: Technology, Testing and Reliability", IEEE Press (1997). [0008] In particular, dual-port SRAM-based FIFOs typically utilize separate read and write pointers to advantageously allow read and write operations to occur independently of each other and achieve fast fall-through capability since data written into a dual-port SRAM FIFO can be immediately accessed for reading. Since these read and write operations may occur independently, independent read and write clocks having different frequencies may be provided to enable the FIFO to act as a buffer between peripheral devices operating at different rates. Unfortunately, a major disadvantage of typical dual-port SRAM-based FIFOs is the relatively large unit cell size for each dual-port SRAM cell therein. Thus, for a given semiconductor chip size, dual-port buffer memory devices typically provide less memory capacity relative to single-port buffer memory devices. For example, using a standard DRAM cell as a reference unit cell consuming one (1) unit of area, a single-port SRAM unit cell typically may consume four (4) units of area and a dual-port SRAM unit cell typically may consume sixteen (16) units of area. Moreover, the relatively large unit cells of a dual-port SRAM FIFO may limit the degree to which the number of write operations can exceed the number of read operations, that is, limit the capacity of the FIFO. [0009] To address these limitations of dual-port buffer memory devices, single-port buffer memory devices have been developed to, among other things, achieve higher data capacities for a given semiconductor chip size. For example, U.S. Pat. No. 5,546,347 to Ko et al. entitled "Interleaving Architecture And Method For A High Density FIFO", assigned to the present assignee, discloses a memory device which has high capacity and uses relatively small single-port memory cells. However, the use of only single port memory cells typically precludes simultaneous read and write access to data in the same memory cell, which means that single-port buffer memory devices typically have slower fall-through time than comparable dual-port memory devices. Moreover, single-port buffer memory devices may use complicated arbitration hardware to control sequencing and queuing of reading and writing operations. [0010] U.S. Pat. No. 5,371,708 to Kobayashi also discloses a FIFO memory device containing a single-port memory array, a read data register for holding read data from the memory array and a write data register for holding write data to the memory array. A bypass switch is provided for transferring data from the write data register to the read data register so that the memory array can be bypassed during testing of the FIFO to detect the presence of defects therein. However, like the above-described single-port buffer memory devices, simultaneous read and write access to data is not feasible. [0011] Commonly assigned U.S. Pat. Nos. 5,978,307, 5,982,700 and 5,999,478 disclose memory buffers having fast fall-through capability. These memory buffers contain a tri-port memory array of moderate capacity having nonlinear columns of tri-port cells therein which collectively form four separate registers, and a substantially larger capacity supplemental memory array (e.g., DRAM array) having cells therein with reduced unit cell size. The tri-port memory array has a read port, a write port and a bidirectional input/output port. The tri-port memory array communicates internally with the supplemental memory array via the bidirectional input/output port and communicates with external devices (e.g., peripheral devices) via the read and write data ports. Efficient steering circuitry is also provided by a bidirectional crosspoint switch that electrically couples terminals (lines IO and IOB) of the bidirectional input/output port in parallel to bit lines (BL and BLB) in the supplemental memory array during a write-to-memory time interval and vice versa during a read-from-memory time interval. Commonly assigned U.S. Pat. No. 6,546,461 also discloses FIFO memory devices that use multiple multi-port caches to support high rate reading operations. [0012] In order to increase the capacity of FIFO memory devices, multiple FIFO memory devices may be cascaded in a depth expansion configuration. As illustrated by FIG. 1A, a pair of FIFO memory devices may be configured to provide a higher capacity FIFO system 10. In this system 10, both devices operate in a conventional first-word fall-through (FWFT) mode. When disposed in the FWFT mode (pin FWFT=Vdd), the output ready pin (/OR) is used to indicate whether or not there is valid data at the data outputs (On) and the input ready pin (/IR) is used to indicate whether or not a FIFO memory device has any free space to support a writing operation. In the FWFT mode, the first word written to an empty FIFO memory device goes directly to the corresponding data outputs (On) after three rising edges of the read clock (RCLK) and any requirement that the read enable signal (/REN) be low to produce output data is not necessary. [0013] The FIFO memory device on the left side of FIG. 1A has a write interface and a read interface. The write interface receives a write clock signal WCLK, a write enable signal (/WEN) and input data (Dn) and generates the input ready flag (/IR). The read interface receives a read clock signal RCLK and a read enable signal (/REN) and generates an output ready flag (/OR) and output data (On). This output ready flag (/OR) may be used as the write enable input signal (/WEN) to the next stage in the cascaded arrangement. The read interface of the left FIFO memory device is electrically coupled to a write interface of the FIFO memory device on the right side of FIG. 1A and the read and write clock signal pins at these interfaces receive a transfer clock (TRANSFER CLOCK). This transfer clock may be an independent clock signal or may constitute the write clock signal or read clock signal. A transfer clock signal operating a maximum frequency is preferred. However, if the write or read clock signal is used in place of the transfer clock signal, then the read or write clock signal having the higher frequency should be used. The read interface of the right FIFO memory device can be electrically coupled to a downstream peripheral device (not shown) or other device or system. [0014] Unfortunately, the ability to increase the capacity of FIFO memory devices operating in the FWFT mode of operation does not translate to FIFO memory devices that are configured to operate in standard mode, which is another conventional mode of operation. This is because an empty flag (/EF) generated at an output of a FIFO memory device in standard mode may not be used as a write enable signal (/WEN) to the next stage in a cascaded arrangement. This is because there is a one cycle difference between the empty flag (/EF) and the output ready flag (/OR) when a FIFO memory device is disposed in the standard mode and FWFT mode, respectively. This one cycle difference in flag generation precludes reliable operation of a depth expansion arrangement of FIFO memory devices when they are disposed in the standard mode. Thus, as illustrated by FIG. 1B, a FIFO memory device 12 that is disposed in a conventional standard mode (pin FWFT=GND) cannot be arranged in a depth expansion configuration. [0015] FIG. 2 illustrates a conventional multi-Q FIFO memory system 100 having a plurality of multi-Q first-in first-out (FIFO) memory chips therein. These chips, which are identified by the labels Device 1, Device 2, . . . , Device n, are responsive to respective ID codes, which are shown as 3-bit codes ID1[2;0], ID2[2:0], . . . , IDn[2:0]. Because these 3-bit codes are unique to each device, the multi-Q FIFO memory system 100 is limited to a maximum of 2.sup.3=8 devices, which provides for a queue expansion of up to a maximum of 256 queues for the case where the write and read addresses (WRADD, RDADSD) are 8-bits wide and a maximum of 32 queues (2.sup.(8-3)) can be allocated within each device. These and other aspects of the FIFO memory system 100 are illustrated and described at page 79 and elsewhere in the aforementioned U.S. Provisional Application Ser. No. ______, filed Jan. 10, 2005. SUMMARY OF THE INVENTION [0016] Multi-Q FIFO memory systems according to embodiments of the present invention include a plurality of multi-Q first-in first-out (FIFO) memory chips electrically coupled to a data output bus. The plurality of multi-Q FIFO memory chips, which are responsive to respective identification codes ID and respective read chip select signals (/RCS), are configured to support an enhanced multi-chip expansion mode of operation. This expansion mode of operation uses the read chip select signals to control one-at-a-time access of at least two selected multi-Q FIFO memory chips receiving equivalent ID codes and equivalent read addresses to the output data bus during read operations. This one-at-a-time access is achieved because the read chip select signals dispose all but a selected one of the plurality of multi-Q FIFO memory chips in a high impedance output mode (to the output bus) during a read operation. The multi-Q FIFO memory chips are also configured so that a most significant portion of a read address is compared to the ID codes associated with the plurality of multi-Q FIFO memory chips to detect multiple equivalencies therebetween during a read operation. This allowance for multiple equivalencies supports greater queue expansion relative to FIFO memory systems requiring uniqueness between an ID code of a chip and a most significant portion of the read address. [0017] Still further embodiments of the present invention include methods of operating a depth-expanded system of multi-Q FIFO memory chips coupled to a common data output bus. These methods include comparing bits (e.g., most significant bits) of an applied read address to ID codes associated with the multi-Q FIFO memory chips to thereby identify a plurality of equivalencies (i.e., identify a plurality of the multi-Q FIFO memory chips as candidates to undergo a read operation). A step is then performed to deselect all but one of the candidate multi-Q FIFO memory chips using a plurality of read chip select signals to dispose data output ports of the deselected multi-Q FIFO memory chips in high impedance states that preclude competing use of the output bus. BRIEF DESCRIPTION OF THE DRAWINGS [0018] FIG. 1A illustrates a pair of conventional FIFO memory devices that are arranged in a depth expansion configuration and support conventional first-word fall-through (FWFT) mode operation. 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