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  Multi-modulus divider retiming circuitUSPTO Application #: 20080042697Title: Multi-modulus divider retiming circuit Abstract: A multi-modulus divider (MMD) receives an MMD input signal and outputs an MMD output signal SOUT. The MMD includes a chain of modulus divider stages (MDSs). Each MDS receives an input signal, divides it by either two or three, and outputs the result as an output signal. Each MDS responds to its own modulus control signal that controls whether it divides by two or three. In one example, a sequential logic element outputs SOUT. The low jitter modulus control signal of one of the first MDS stages of the chain is used to place a sequential logic element into a first state. The output signal of one of the MDS stages in the middle of the chain is used to place the sequential logic element into a second state. Power consumption is low because the sequential logic element is not clocked at the high frequency of the MMD input signal. (end of abstract) Agent: Qualcomm Incorporated - San Diego, CA, US Inventors: Chiewcharn Narathong, Wenjun Su USPTO Applicaton #: 20080042697 - Class: 327115 (USPTO) The Patent Description & Claims data below is from USPTO Patent Application 20080042697. Brief Patent Description - Full Patent Description - Patent Application Claims
CROSS-REFERENCE TO RELATED APPLICATION [0001]This application claims the benefit under 35 U.S.C. .sctn. 119 of Provisional Application Ser. No. 60/833,156, filed Jun. 28, 2006, said provisional application is incorporated herein by reference. BACKGROUND [0002]1. Technical Field [0003]The disclosed embodiments relate to multi-modulus dividers (MMDs). [0004]2. Background Information [0005]The receiver and transmitter circuitry within a cellular telephone typically includes one or more local oscillators. Such a local oscillator may, for example, include a phase-locked loop (PLL) that receives a stable but relatively low frequency signal (for example, 20 MHz) from a crystal oscillator and generates the output signal of the selected relatively high frequency (for example, 900 MHz). The feedback loop of the PLL includes a frequency divider that receives the high frequency signal and divides it down to obtain a low frequency signal that is of the same phase and frequency as the signal from the crystal oscillator. [0006]A type of divider referred to here a "multi-modulus divider" (MMD) is often used to realize the frequency divider. The MMD receives the high frequency input signal SIN and divides it by a divisor value DV to generate the low frequency output signal SOUT. The MMD includes a plurality of modulus divider stages (MDSs) that are chained together to form the MMD. Each MDS (except the last MDS) receives a feedback modulus control signal from the next MDS in the chain. Each MDS also receives a modulus divisor control signal S. If the modulus divisor control signal S for a particular MDS has a first digital logic value then the MDS operates in a divide-by-two mode, otherwise the MDS operates in a divide-by-three mode. The modulus divisor control signal values S of the various MDS stages of the MMD together determine the divisor value DV by which the MMD divides. [0007]In many MMD applications, the MMD output signal is to have a duty cycle of approximately fifty percent. The output signal is also to have low jitter with respect to the high frequency MMD input signal. Each MDS stage introduces an amount of jitter. Due to the cascading of the MDS stages, the jitter of the various MDS stages of the MMD accumulates. In one cellular telephone application involving a cellular telephone standard, using the output of the last MDS as the MMD output results in so much accumulated jitter that the noise requirement imposed on the MMD by the cellular telephone standard cannot be satisfied. [0008]One conventional way to solve this problem is to use the jitter-free high frequency MMD input signal to synchronize (to "reclock") the jittery low frequency MMD output signal with a high speed flip-flop. This makes the output of the flip-flop almost jitter free. This solution, however, generally requires a well-defined phase relationship between the high frequency MMD input signal and the low frequency MMD output signal. Due to the MMD architecture, it may be difficult to maintain an adequately constant phase relationship between the two signals when the divisor value DV is large. [0009]A second conventional way to solve the jitter problem involves three flip-flops. The first flip-flop synchronizes the modulus control signal that controls the first MDS stage with the high frequency MMD input signal. The modulus control signal is the signal that determines whether the first MDS stage divides by two or divides by three. The synchronized output of the first flip-flop is supplied to the clock input of the second flip-flop. The D-input of the second flip-flop is coupled to receive a fixed digital logic high value so that an edge of the synchronized output of the first flip-flop clocks the digital logic high value into the second flip-flop. The reset input of the second flip-flop is coupled to receive a reset signal that is a logical combination of several signals output from several of the MDSs in the middle of the MMD. The reset signal therefore resets the second flip-flop to a digital logic low. The output of the second flip-flop is supplied to the D-input of the third flip-flop and the third flip-flop is clocked using the high frequency MMD input signal so as to synchronize the output of the second flip-flop with the high frequency MMD input signal. The reset input of the third flip-flop is coupled to receive the reset signal. The Q output of the third flip-flop outputs the desired low-jitter low frequency signal that has a duty cycle of approximately fifty percent. Unfortunately, this second conventional solution consumes a large amount of power because two of the three flip-flops are being clocked by the high frequency MMD input signal. Power consumption is therefore undesirably high. SUMMARY [0010]A multi-modulus divider (MMD) receives an MMD input signal, divides it by a divisor value, and outputs an MMD output signal SOUT. The MMD includes a novel retiming circuit (for example, a sequential logic element) and a chain of modulus divider stages (MDSs). Each MDS receives an input signal, frequency divides it by two or by three, and outputs the result as an output signal. Each MDS responds to its own modulus control signal that controls whether the MDS divides by two or divides by three. The sequential logic element outputs the MMD output signal SOUT. The modulus control signal of one of the first MDS stages of the chain is used to place the sequential logic element into a first state. The output signal of one of the MDS stages in the middle of the chain is used to place the sequential logic element into a second state. In one example, the sequential logic element is a flip-flop. The modulus control signal sets the flip-flop so that the flip-flop is in the "set" state and asserts the output signal SOUT to a digital logic high value. The output signal of the MDS in the middle of the chain resets the flip-flop so that the flip-flop is in the "reset" state and deasserts the output signal SOUT to a digital logic low value. [0011]It is recognized that the modulus control signal that is used to place the sequential logic element into the first state has a small amount of accumulated jitter with respect to the MMD input signal. The modulus control signal is gated by the low jitter output signal of a MDS early in the chain. Because edges of pulses of this modulus control signal have low jitter, the corresponding edges of the output signal SOUT also have low jitter. Moreover, it is also recognized that the output signal of one of the MDS stages transitions approximately halfway between edges of the modulus control signal. This one MDS stage output signal is therefore used to place the sequential logic element back into the second state approximately midway between each pair of adjacent pulses of the modulus control signal so that the output signal SOUT has a duty cycle of approximately 50/50. [0012]In one advantageous aspect, the sequential logic element that generates the output signal SOUT is not clocked at the high frequency of the MMD input signal. The signals that set and reset the sequential logic element have longer minimum pulsewidths than the MMD input signal. Accordingly, the novel retiming circuit consumes significantly less power than does a conventional retiming circuit that uses the higher frequency MMD input signal to retime the MMD output signal. [0013]The foregoing is a summary and thus contains, by necessity, simplifications, generalizations and omissions of detail; consequently, those skilled in the art will appreciate that the summary is illustrative only and does not purport to be limiting. Other aspects, inventive features, and advantages of the devices and/or processes described herein, as defined solely by the claims, will become apparent in the non-limiting detailed description set forth herein. BRIEF DESCRIPTION OF THE DRAWINGS [0014]FIG. 1 is a simplified diagram of a mobile communication device (in this example, a cellular telephone) in accordance with one novel aspect. [0015]FIG. 2 is a diagram of the RF transceiver integrated circuit within the mobile communication device of FIG. 1. [0016]FIG. 3 is a diagram of a local oscillator in the RF transceiver integrated circuit of FIG. 2. [0017]FIG. 4 is a diagram of the frequency divider of the local oscillator of FIG. 3. The frequency divider is a multi-modulus divider (MMD). The diagram is a conceptual diagram using logic gate symbols. [0018]FIG. 5 sets forth an equation that indicates what the value of S[6:0] should be in order for the seven-stage MMD of FIG. 4 to divide by a desired divisor. [0019]FIG. 6 is a conceptual diagram of one MDS of the MMD of FIG. 4. [0020]FIG. 7 is a waveform diagram that illustrates an operation of the MMD of FIG. 4. Continue reading... Full patent description for Multi-modulus divider retiming circuit Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Multi-modulus divider retiming circuit patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. 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