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  Multi-layer film stack for extinction of substrate reflections during patterningUSPTO Application #: 20060086954Title: Multi-layer film stack for extinction of substrate reflections during patterning Abstract: A method including introducing a dielectric layer over a substrate between an interconnection line and the substrate, the dielectric layer comprising a plurality of alternating material layers; and patterning an interconnection to the substrate. An apparatus comprising a substrate comprising a plurality of devices formed thereon; and an interlayer dielectric layer comprising a base layer and a cap layer, the cap layer comprising a plurality of alternating material layers overlying the substrate. (end of abstract) Agent: Blakely Sokoloff Taylor & Zafman - Los Angeles, CA, US Inventors: Sanjay S. Natarajan, Sean W. King, Khaled A. Elamrawi USPTO Applicaton #: 20060086954 - Class: 257213000 (USPTO) Related Patent Categories: Active Solid-state Devices (e.g., Transistors, Solid-state Diodes), Field Effect Device The Patent Description & Claims data below is from USPTO Patent Application 20060086954. Brief Patent Description - Full Patent Description - Patent Application Claims
CROSS-REFERENCE TO RELATED APPLICATION [0001] This application is a divisional of co-pending U.S. patent application Ser. No. 09/750,734, filed Dec. 27, 2000. BACKGROUND [0002] 1. Background [0003] Modern integrated circuits use interconnections to connect the individual devices on a chip or to send and/or receive signals external to the chip. Popular types of interconnections include aluminum or copper interconnections (lines) coupled to devices, including other interconnections (lines) by interconnections through vias. [0004] 2. Field of the Invention [0005] The invention relates to integrated circuit fabrication and, more particularly, to the definition and alignment of interconnections in integrated circuit structures. [0006] Fabricating an interconnection structure to a device formed on a circuit substrate, such as an interconnection to a transistor device, typically involves introducing a photoimageable material (e.g., photoresist) over a dielectric layer insulating the device. The photoimageable material is patterned to have an opening to the dielectric above the desired point of contact for the subsequent interconnection. An etch is then used to form an opening or via through the dielectric layer to the device. [0007] One problem with the current state of the art photoimaging technique is the formation of undesired openings in the photoimageable material due to substrate reflections of light. FIG. 1 illustrates the light scattering effect according to conventional processing. FIG. 1 shows structure 100 including substrate 110 of, for example, a semiconductor material such as silicon. Substrate 110 has, in this example, transistor devices 120 formed in active areas of the substrate. The active areas are separated from one another by shallow trench isolation (STI) 130. Dielectric material 135 such as, for example, silicon dioxide (SiO.sub.2) overlies devices 120 and substrate 110. Photoimageable material 140 such as a positive photoresist overlies dielectric material 135. In this example, an opening in photoimageable material is desired over area 150 which will be an opening for a via to transistor device 120. [0008] Referring to FIG. 1, it is shown that light directed through opening area 150 in the process of developing the photoimageable material may scatter within structure 110 and reflect off structures on substrate 110 (i.e., substrate reflections). Certain structures, such as gate electrodes and STI 130 are sufficiently reflective to reflect the scattered light and create undesired developed areas in photoimageable material 140. FIG. 1 shows undesired opening area 180 formed by reflective light 160 off a gate electrode and reflective light 170 off STI 130. Upon developing the photoimageable material, the undesired opening area 180 may be developed in such a way to create an opening to photoimageable material to dielectric material 135. [0009] By creating undesired openings in the photoimageable material, failure modes are introduced into the circuit device processing. When these openings are later filled with interconnection material, electrical shorts may be introduced either between metal lines or on the silicon structure. Further, undesired interconnects coupled to silicon surface introduce a capacitive element in the structure. [0010] Attempts to remedy the problem of creating undesired opening areas include placing an anti-reflective coating over the structure. Such technique, however, involves introducing an additional film which adds process cost and complexity and possibly additional defects in the process flow. Reduction of the light intensity is not a workable solution at this point as it requires approximately 27 milliJoules (mJ) to develop positive photoresist with only one to two milliJoules margin. Therefore, reducing the light intensity may result in the loss of the desired opening area, such as opening area 150. [0011] What is needed are improved processing techniques and an improved structure that suppresses undesired reflections. BRIEF DESCRIPTION OF THE DRAWINGS [0012] FIG. 1 shows a schematic, cross-sectional view of a portion of a prior art integrated circuit substrate and illustrates light reflections through a photoimageable material opening. [0013] FIG. 2 shows a cross-sectional view of a portion of an integrated circuit structure including a substrate having circuit devices formed thereon, an etch stop layer overlying the substrate followed by a base dielectric material and two alternating layers of dielectric material according to an embodiment of the invention. [0014] FIG. 3 shows the structure of FIG. 2 after the introduction of two additional alternating layers of dielectric material. [0015] FIG. 4 shows the structure of FIG. 3 after the introduction of two additional alternating layers. [0016] FIG. 5 shows the structure of FIG. 4 after the introduction of three additional alternating layers. [0017] FIG. 6 shows the structure of FIG. 5 after the introduction and patterning of a photoimageable material having openings to devices in the substrate. [0018] FIG. 7 shows the structure of FIG. 6 after introducing an interconnection to a contact point on the substrate. [0019] FIG. 8 is a graphical representation of the peak reflectance through a prior art substrate structure and a structure according to FIG. 5. DETAILED DESCRIPTION OF THE INVENTION [0020] The invention relates to techniques and an apparatus for forming interlayer dielectric material layers that suppress undesired substrate reflections. In one embodiment, a method includes introducing a dielectric layer over a substrate between an interconnection line and a contact point, the dielectric layer comprising a plurality of different material layers, and patterning an interconnection to the contact point. An embodiment of the apparatus includes a substrate comprising a plurality of devices formed thereon and a dielectric layer comprising a plurality of alternating material layers overlying the substrate. The apparatus also includes an interconnection line overlying the dielectric layer and coupled to at least one of the plurality of devices. Continue reading... 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