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Multi-format consistency checking toolMulti-format consistency checking tool description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20080263487, Multi-format consistency checking tool. Brief Patent Description - Full Patent Description - Patent Application Claims As IC design evolves, tools are created to solve new design challenges. These tools produce new and different formats to represent the design. When this occurs, conventional tools lack the ability to check the consistency of a design encoded in several different design representations. It would be desirable to implement a method, system, and tool that is able to perform syntax and semantic checks for and against a wide variety of design representations. BRIEF DESCRIPTION OF THE DRAWINGSThe teachings described herein can be readily understood by considering the following detailed description in conjunction with the accompanying drawings. Like reference numerals are used for like elements in the accompanying drawings. FIG. 1 is a block diagram of a data processing system incorporating a consistency checker. FIG. 2 is a block diagram showing details of the consistency checker of FIG. 1. FIG. 3 is a flowchart showing a method of consistency checking. FIGS. 4(a) and 4(b) are flow charts showing a method of initializing a consistency checker, wherein a user can change the type of designs to be checked and can further change the terms included in rules of the checker. FIG. 5 shows an example of a user interface that allows a user to select rules to use during consistency checking. FIG. 6 shows an example user interface that allows a user to add a new term to a rule set. FIG. 7(a) shows a portion of an example design representation written in the C programming language. FIG. 7(b) shows a portion of an example design representation written in the Verilog hardware description language. FIG. 8(a) is a flowchart showing an example abstraction function used in a translator for design types of the C programming language. FIG. 8(b) is a flowchart showing an example abstraction function used in the translator for design types of the Verilog hardware description language. The figures depict embodiments for purposes of illustration only. One can recognize from the following discussion that alternative embodiments of the structures and methods illustrated herein may be employed without departing from the principles described herein. DETAILED DESCRIPTION OF EMBODIMENTSContinue reading about Multi-format consistency checking tool... Full patent description for Multi-format consistency checking tool Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Multi-format consistency checking tool patent application. ### 1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. Start now! - Receive info on patent apps like Multi-format consistency checking tool or other areas of interest. ### Previous Patent Application: Method and apparatus for small die low power system-on-chip design with intelligent power supply chip Next Patent Application: Optical proximity correction method, optical proximity correction apparatus, and optical proximity correction program, method of manufacturing semiconductor device, design rule formulating method, and optical proximity correction condition calculating met Industry Class: Data processing: design and analysis of circuit or semiconductor mask ### FreshPatents.com Support Thank you for viewing the Multi-format consistency checking tool patent info. IP-related news and info Results in 0.06117 seconds Other interesting Feshpatents.com categories: Novartis , Pfizer , Philips , Polaroid , Procter & Gamble , 174 |
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