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  Multi-chip ball grid array packageUSPTO Application #: 20060194366Title: Multi-chip ball grid array package Abstract: A multi-chip BGA package has two or more rerouted chips, each of which has one or more electrode plates. The electrode plate is coplanar with rerouting lines on the rerouted chip and may act as a decoupling capacitor, reducing simultaneous switching noise from fluctuations in power voltage, without causing an increase in thickness of the package. Further, each pair of rerouting lines on upper and lower rerouted chips includes two or more interconnection bumps. This reduces inductance and resistance of electric signal propagation. Therefore, the multi-chip BGA package of this invention can realize small, thin, high-speed and high-density memory devices. (end of abstract) Agent: Marger Johnson & Mccollom, P.C. - Portland, OR, US Inventors: Jong-Joo Lee, Dong-Ho Lee USPTO Applicaton #: 20060194366 - Class: 438106000 (USPTO) Related Patent Categories: Semiconductor Device Manufacturing: Process, Packaging (e.g., With Mounting, Encapsulating, Etc.) Or Treatment Of Packaged Semiconductor The Patent Description & Claims data below is from USPTO Patent Application 20060194366. Brief Patent Description - Full Patent Description - Patent Application Claims
CROSS REFERENCE TO RELATED APPLICATIONS [0001] This application is a Divisional of U.S. Pat. No. 10/828,792, filed on Apr. 20, 2004, now pending, which claims priority from Korean Patent Application Nos. 2003-26581 filed Apr. 26, 2003, which are herein incorporated by reference in their entirety. BACKGROUND OF THE INVENTION [0002] 1. Field of the Invention [0003] The present invention relates generally to a multi-chip package with ball grid array (BGA), and more particularly, to a multi-chip BGA package with improved rerouting configuration for better signal propagation and decoupling capacitors for reduced switching noise. [0004] 2. Description of the Related Art [0005] Multi-chip packaging involves mounting two or more chips on a lead frame or a circuit board, specifically, a BGA multi-chip package employs conductive balls arranged to provide electrical connections with external electronics. [0006] FIG. 1 shows an exemplary conventional multi-chip BGA package. Referring to FIG. 1, the multi-chip BGA package M1 includes lower and upper rerouted chips 10 and 20, interconnection bumps 5, a substrate 1, conductive balls 2, bonding wires 3, and an encapsulant 4. [0007] The lower and upper rerouted chips 10 and 20 are spaced apart with active surfaces facing each other. Each rerouted chip 10 and 20 has a semiconductor chip 11 and 21, a first insulating layer 13 and 23, rerouting lines 14 and 24, and a second insulating layer 17 and 27. [0008] Each semiconductor chip 11 and 21 is a center pad type. That is, chip pads 12 and 22 are arranged in a row along central lines on the active surface of each chip 11 and 21. The chip pads 12 and 22 protrude through a passivation layer (not shown) covering the active surface and made chiefly of silicon nitride. [0009] The first insulating layer 13 and 23 of each rerouted chip 10 and 20 is on a passivation layer, exposing chip pads 12 and 22. The rerouting lines 14 and 24, also called redistribution lines, are formed on the first insulating layer 13 and 23 and electrically connect with respective chip pads 12 and 22. The rerouting lines 14 and 24 extend perpendicular to a row of the chip pads 12 and 22 and alternately reach opposing edges of the chip. [0010] The second insulating layer 17 and 27 covers both the first insulating layer 13 and 23 and the rerouting lines 14 and 24, exposing bump pads 15 and 25 which are integrated in the rerouting lines 14 and 24. The second insulating layer 17 of the lower chip 10 exposes bond pads 16. [0011] Each interconnection bump 5 resides between corresponding lower and upper bump pads 15 and 25 and electrically connects the corresponding lower and upper rerouting lines 14 and 24. [0012] The top surface of substrate 1 attaches to the back surface of lower chip 10 by adhesion. Conductive balls 2 arrange across the bottom surface of substrate 1 and electrically connect the package M1 to external electronics. [0013] Bonding wires 3 electrically connect bond pads 16 of lower chip 10 to substrate 1. The encapsulant 4 provides the top surface of substrate 1 and covers the chips 10 and 20 and bonding wires 3. [0014] The above-described conventional multi-chip BGA package 1 has drawbacks. For example, an increase in switching speed of the rerouted chip causes simultaneous switching noise due to fluctuation in chip power voltage. This often decreases chip speed, increases noise-like fluctuation and time distortion, as well as increasing other operation errors. Furthermore, when connecting a cable shield to a ground line, common-mode radiation occurs and serious electromagnetic interference (EMI) follows. Additionally, complicated interconnection schemes in conventional multi-chip BGA packages increase parasitic inductance and deteriorate electric signal propagation. SUMMARY OF THE INVENTION [0015] It is therefore an object of the present invention to provide a multi-chip BGA package that reduces switching noise, improves signal propagation, and generally improves electronic characteristics. [0016] In one embodiment of the present invention, a multi-chip BGA package comprises first and second rerouted chips. The first rerouted chip includes a first semiconductor chip, first rerouting lines, and a first electrode plate. Additionally, it has first chip pads composed of first power chip pads and first ground chip pads. The first rerouting lines electrically connect to the first chip pads. The first electrode plate on the first semiconductor chip electrically connects to the first power chip pads or the first ground chip pads. [0017] The second rerouted chip, which faces the first rerouted chip, includes a second semiconductor chip, second rerouting lines, and a second electrode plate. Additionally, it has second chip pads composed of second power chip pads electrically connected to the first power chip pads and second ground chip pads electrically connected to the first ground chip pads. The second rerouting lines electrically connect to the second chip pads. The second electrode plate on the second semiconductor chip electrically connects to the second power chip pads or the second ground chip pads. [0018] In particular, when the first electrode plate connects to the first power chip pads, the second electrode plate connects to the second ground chip pads, alternatively, when the first electrode plate connects to the first ground chip pads, the second electrode plate connects to the second power chip pads. [0019] The multi-chip BGA package further comprises a plurality of first interconnection bumps, a substrate, a plurality of bonding wires, and a plurality of conductive balls. The first interconnection bumps interpose and electrically connect the first rerouting lines and the second rerouting lines. The substrate supports the first rerouted chip. The bonding wires electrically connect the first rerouting lines with the substrate. The conductive balls are arranged under the substrate and also electrically connect the substrate to external electronics. [0020] In another embodiment, the first rerouted chip may further include a first insulating layer on the first semiconductor chip, buttressing the first electrode plate. The first insulating layer may have first openings through which the first electrode plate communicates with the first power chip pads or the first ground chip pads. Moreover, the first electrode plate may be coplanar with the first rerouting lines and may have first slots, which may contain the first rerouting lines. In particular, the first rerouting lines may have a coplanar waveguide capable of impedance control according to a ratio of a width of the first rerouting line to a width of the first slot. [0021] In still another embodiment, the second rerouted chip may further include a second insulating layer on the second semiconductor chip, buttressing the second electrode plate. The second insulating layer may have second openings through which the second electrode plate communicates with the second power chip pads or the second ground chip pads. Moreover, the second electrode plate may be coplanar with the second rerouting lines and may have second slots, which may contain the second rerouting lines. In particular, the second rerouting lines may have a coplanar waveguide capable of impedance control according to a ratio of a width of the second rerouting line to a width of the second slot. Continue reading... Full patent description for Multi-chip ball grid array package Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Multi-chip ball grid array package patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. 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