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05/31/07 - USPTO Class 174 |  92 views | #20070119616 | Prev - Next | About this Page  174 rss/xml feed  monitor keywords

Mounting substrate, manufacturing method of mounting substrate and manufacturing method of semiconductor device

USPTO Application #: 20070119616
Title: Mounting substrate, manufacturing method of mounting substrate and manufacturing method of semiconductor device
Abstract: A mounting substrate for mounting a semiconductor chip, having a plurality of passive elements which are connected to the semiconductor chip and are formed to be mutually electrically-independent, and a wiring part including a plurality of via plugs respectively independently connected to the plurality of passive elements and pattern wiring connected to the via plugs, wherein the wiring part is constructed so that a state of connection between the semiconductor chip and the plurality of passive elements can be changed by changing the pattern wiring. (end of abstract)



Agent: Drinker Biddle & Reath (dc) - Washington, DC, US
Inventors: Yasuyoshi Horikawa, Tomoo Yamasaki
USPTO Applicaton #: 20070119616 - Class: 174250000 (USPTO)

Related Patent Categories: Electricity: Conductors And Insulators, Conduits, Cables Or Conductors, Preformed Panel Circuit Arrangement (e.g., Printed Circuit)

Mounting substrate, manufacturing method of mounting substrate and manufacturing method of semiconductor device description/claims


The Patent Description & Claims data below is from USPTO Patent Application 20070119616, Mounting substrate, manufacturing method of mounting substrate and manufacturing method of semiconductor device.

Brief Patent Description - Full Patent Description - Patent Application Claims
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TECHNICAL FIELD

[0001] The present disclosure relates to a mounting substrate which mounts a semiconductor chip and has a passive element connected to the semiconductor chip, and a semiconductor device made by mounting a semiconductor chip on the mounting substrate.

RELATED ART

[0002] In recent years, various structures in which a passive element of a semiconductor chip is built into a semiconductor device with miniaturization and thinning of a semiconductor device (semiconductor package) for mounting a semiconductor chip have been proposed.

[0003] For example, one example of the passive element includes a thin film capacitor. The thin film capacitor is connected to a semiconductor chip and is used in various uses and may be used as, for example, a decoupling capacitor for stabilizing an action by suppressing variations in power source voltage of the semiconductor chip.

[0004] For example, FIGS. 10A to 10D show one example of a manufacturing method of a mounting substrate of a semiconductor chip into which a passive element is built by following a procedure.

[0005] First, in a step shown in FIG. 10A, a capacitor 12 made by forming a dielectric part 14 between a second electrode part 13 and a first electrode part 15 is formed on a substrate 11. In this case, an electrode pad 13A may be formed on the second electrode part 13 extending outside the dielectric part 14 and also an electrode pad 15A may be formed on the first electrode part 15. Further, an insulating layer 16 is formed so as to cover the capacitor 12 and a passive element substrate 10 made by installing the capacitor is formed.

[0006] Next, in a step shown in FIG. 10B, the passive element substrate 10 is installed on an insulating layer 23 formed on a substrate 21. Also, a wiring part 22 covered with the insulating layer 23 is formed on the substrate 21. Also, a wiring part 24 made of a via plug connected to the wiring part 22 and pattern wiring connected to the via plug is formed in the insulating layer 23.

[0007] Then, in a step shown in FIG. 10C, an insulating layer (a build-up resin layer) 25 is formed so as to cover the passive element substrate 10 and the wiring part 24. Thereafter, a via hole 25C reaching the wiring part 24, a via hole 25A reaching the electrode pad 13A and a via hole 25B reaching the electrode pad 15A are respectively formed by, for example, a laser with respect to the insulating layer 25.

[0008] Then, in a step shown in FIG. 10D, a wiring part 26 made of a via plug formed in the via hole 25A and pattern wiring connected to the via plug, a wiring part 27 made of a via plug formed in the via hole 25B and pattern wiring connected to the via plug, and a wiring part 28 made of a via plug formed in the via hole 25C and pattern wiring connected to the via plug are respectively formed by, for example, a semi-additive method.

[0009] In this manner, the mounting substrate into which the passive element (for example, a capacitor) is built can be formed.

[0010] [Patent Reference 1] Japanese Patent Unexamined Publication No. 7-30258

[0011] [Patent Reference 2] Japanese Patent Unexamined Publication No. 8-181453

[0012] [Patent Reference 3] Japanese Patent Unexamined Publication No. 2005-72311

[0013] [Patent Reference 4] Japanese Patent Unexamined Publication No. 2005-191266

[0014] However, the related-art mounting substrate into which the passive element such as the capacitor is built had a problem that it is difficult to adjust (tune) characteristics of the passive element.

[0015] For example, in the case of a passive element built-in type substrate, the built-in passive element may be affected by resistance, parasitic capacitance or parasitic induction, etc. generated by installation etc. of wiring etc. connected. As a result of this, there were cases where the intended characteristics cannot be obtained when the passive element is connected to a semiconductor chip. In this case, when the passive element is exposed to the surface, there are cases where the characteristics can be adjusted by, for example, laser trimming, but when the passive element is built in, it becomes difficult to make these adjustments.

[0016] Also, in the passive element built-in type mounting substrate, it is necessary to route the wiring complicatedly and it is difficult to previously predict the characteristics as compared with wiring of a surface mounting type. As a result of this, in some cases, the need for a repeat of design, prototyping and evaluation in order to manufacture the final product arises.

[0017] For example, in Patent Reference 1 (Japanese Patent Unexamined Publication No. 7-30258) described above, a method for improving a yield of a mounting substrate by forming a plurality of electrodes of capacitors built into the mounting substrate and excluding the short-circuited capacitors (electrodes) from the connection is disclosed. However, in the method, a concrete method for adjusting characteristics of the capacitors is not disclosed.

[0018] Also, in Patent Reference 2 (Japanese Patent Unexamined Publication No. 8-181453) described above, a method for selecting a capacitor connected on the uppermost layer in a mounting substrate into which a plurality of capacitors with different electrode areas are built is disclosed. However, in the method, one electrode of the capacitor is common and connection of the capacitor is limited to parallel connection and a range of adjustment or freedom of design is not sufficient.

SUMMARY

[0019] Embodiments of the present invention provide a mounting substrate, a manufacturing method of the mounting substrate, and a manufacturing method of a semiconductor device made by mounting a semiconductor chip on the mounting substrate.

[0020] Further, embodiments of the present invention provide a mounting substrate which has a passive element connected to a semiconductor chip and facilitates adjustment of characteristics of the passive element, a manufacturing method of the mounting substrate, and a manufacturing method of a semiconductor device made by mounting a semiconductor chip on the mounting substrate.

[0021] In the first viewpoint of one or more embodiments of the invention, a mounting substrate for mounting a semiconductor chip, comprises a plurality of passive elements which are connected to the semiconductor chip and are formed to be mutually electrically-independent, and a wiring part including a plurality of via plugs respectively independently connected to the plurality of passive elements and pattern wiring connected to the via plugs, wherein the wiring part is constructed so that a state of connection between the semiconductor chip and the plurality of passive elements can be changed by changing the pattern wiring.

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