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Mosfet wth high angle sidewall gate and contacts for reduced miller capacitanceRelated Patent Categories: Semiconductor Device Manufacturing: Process, Making Field Effect Device Having Pair Of Active Regions Separated By Gate Structure By Formation Or Alteration Of Semiconductive Active Regions, Having Insulated Gate (e.g., Igfet, Misfet, Mosfet, Etc.), Self-alignedMosfet wth high angle sidewall gate and contacts for reduced miller capacitance description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20070184621, Mosfet wth high angle sidewall gate and contacts for reduced miller capacitance. Brief Patent Description - Full Patent Description - Patent Application Claims
RELATED APPLICATION [0001] This application is a divisional of U.S. application Ser. No. 11/162,424 filed Sep. 9, 2005. [0002] The present invention relates to an improved field effect transistor (FET), and more particularly to an improved metal-oxide-semiconductor field-effect transistor (MOSFET), having a gate structure with angled sidewalls for reduction of gate-to-source/drain overlap capacitance, and methods for fabricating such an FET device. BACKGROUND OF THE INVENTION [0003] In the semiconductor industry, there is a constant demand to increase the operating speed of integrated circuits (ICs). This increased demand is fueled by the need for electronic devices such as computers to operate at increasingly greater speeds. The demand for increased speed, in turn, has resulted in a continual size reduction of the semiconductor devices. Specifically, the channel length, junction depths, and/or gate dielectric thickness of field effect transistors (FETs) are reduced. Thus, there is a constant drive to reduce the size, or scale, of the components of a typical FET to increase the overall speed of the FET. Additionally, reducing the size, or scale, of the components of a typical FET also increases the density and number of FETS that can be fabricated on a given single semiconductor wafer. [0004] However, reducing the channel length of a transistor also increases "short-channel" effects, as well as "edge effects" that are relatively unimportant in long channel transistors. Short-channel effects include, among other things, an increased source/drain (S/D) leakage current when the transistor is switched "off". One of the edge effects that may influence transistor and circuit performance is known as the total gate-to-drain and gate-to-source capacitance. Gate-drain capacitance is also known as "Miller capacitance" due to a Miller multiplication factor, which increases the capacitance by a factor related to the voltage gain of a transistor. The Miller multiplication further increases the parasitic gate-to-drain capacitance that slows down circuits. As is known to those skilled in the art, a significant portion of gate-to-drain and gate-to-source or Miller capacitance is an overlap capacitance that arises between the gate conductor and the S/D) metal contact. [0005] Coupled with the Miller effect, this overlap capacitance contributes significantly to the overall switching capacitance, which in turn reduces the operation speed of the device. [0006] Therefore, there is a continuing need for reducing the gate-to-source/drain metal contact capacitance in FET devices. SUMMARY OF THE INVENTION [0007] In one aspect, the present invention relates to an FET device, more preferably a (MOSFET), with significantly reduced gate-to-source/drain overlap capacitance. Such an FET device contains angled sidewalls that are characterized by an offset angle that is greater than about 0.degree. and not more than about 45.degree. with respect to a vertical direction. [0008] The term "vertical" as used herein refers to a direction that is normal or perpendicular to the top surface of a semiconductor substrate. [0009] In general terms, the present invention relates to an FET device that comprises: [0010] a semiconductor substrate containing source and drain regions; [0011] a gate dielectric layer located on a top surface of the semiconductor substrate; and [0012] a conductive gate electrode located on the gate dielectric layer, wherein the conductive gate electrode has a top, a base, and sidewalls, wherein the sidewalls of the conductive gate electrode are offset from a vertical direction by an offset angle that is greater than about 0.degree. and not more than about 45.degree., so that the top of said conductive gate electrode has a surface area smaller than that of the base. [0013] The offset angle is preferably between about 5.degree. and about 30.degree., and more preferably between about 10.degree. and about 20.degree.. [0014] The FET device of the present invention preferably further comprises any of the following structures: source extension and drain extension regions in the semiconductor substrate, source/drain spacers along the sidewalls of the conductive gate electrode, metal silicide conductors for the gate electrode, the source region, and the drain region, and a capping layer over the conductive gate electrode, the source region, and the drain region. [0015] Preferably, the FET device of the present invention further comprises metal contacts with angled or offset sidewalls for the source and drain regions. The sidewalls of each metal contact are characterized by offset angles that are larger than 0.degree. but not more than 45.degree. away from the vertical direction, so that the top surface area of the metal contact is larger than its base surface area. [0016] The FET device of the present invention has significantly reduced overlap capacitance, in comparison with conventional FET devices having straight-wall gate electrodes. The gate to source metal contact or gate to drain metal contact overlap capacitance of the FET devices is preferably less than 0.07 femtoFarads per micron of channel width. [0017] In a further aspect, the present invention relates to a method for fabricating the FET device described hereinabove, comprising: [0018] forming a gate dielectric layer over a semiconductor substrate; [0019] forming a gate conductor layer over the gate dielectric layer; [0020] selectively patterning the gate conductor layer to form a conductive gate electrode that has a top, a base, and sidewalls, wherein the sidewalls of the conductive gate electrode are offset from a vertical direction by an offset angle that is greater than about 0.degree. and not more than about 45.degree., so that the top of the conductive gate electrode has a surface area smaller than that of the base; and [0021] forming source and drain regions in the semiconductor substrate. Continue reading about Mosfet wth high angle sidewall gate and contacts for reduced miller capacitance... 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