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Mos transistor with recessed gate and method of fabricating the sameRelated Patent Categories: Semiconductor Device Manufacturing: Process, Making Field Effect Device Having Pair Of Active Regions Separated By Gate Structure By Formation Or Alteration Of Semiconductive Active Regions, Having Insulated Gate (e.g., Igfet, Misfet, Mosfet, Etc.), Including Passive Device (e.g., Resistor, Capacitor, Etc.), Capacitor, Trench CapacitorMos transistor with recessed gate and method of fabricating the same description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20070093021, Mos transistor with recessed gate and method of fabricating the same. Brief Patent Description - Full Patent Description - Patent Application Claims
CROSS-REFERENCE TO RELATED APPLICATION [0001] This application is a Divisional of U.S. patent application Ser. No. 10/884,223, filed on Jul. 1, 2004, now pending, which claims the benefit of Korean Patent Application No. 2003-0056264, filed on Aug. 13, 2003, the disclosure of which is hereby incorporated herein by reference in its entirety. BACKGROUND OF THE INVENTION [0002] 1. Field of the Invention [0003] The present invention relates to a semiconductor device and a method of fabricating the same and, more particularly, to a MOS transistor with a recessed gate and a method of fabricating the same. [0004] 2. Description of the Related Art [0005] In general when the length of a transistor gate is reduced to a level approaching 0.1 .mu.m or thereabout, several problems can occur. The problems that occur include rolling off of the threshold voltage, decrease of the punch-through voltage due to a short channel effect (SCE) and so on. In order to suppress the short channel effect, one can (a) reduce the junction depth of a source and a drain, or (b) increase the effective channel length. The structure of a metal oxide semiconductor (MOS) transistor with a recessed gate is such that it allows one to implement both of the above listed methods at the same time. [0006] FIG. 1 is a plan view of a typical MOS transistor with a recessed gate. Referring to FIG. 1, an active region 11 is defined by a trench isolation layer 11a formed in a semiconductor substrate. A recessed gate 30 is formed to intersect the active region 11. One portion of the active region 11 adjacent to the gate 30 is a source region 13, and another portion of the active region 11 at the other side of gate 30 is a drain region 15. One portion of the active region 11 which is overlapped by the gate 30 is a channel region 17. [0007] FIGS. 2 and 3 are sectional views which illustrate the structure of the MOS transistor taken along the lines of I-I' and II-II' of FIG. 1 respectively. Referring to FIG. 2, the recessed gate 30 is located in a shallow trench formed in a semiconductor substrate 10. The active regions adjacent to the recessed gate 30 are the source region 13 and the drain region 15, and the active region under the recessed gate 30 is the channel region 17. A gate insulating layer 20 is interposed between the recessed gate 30 and the channel region 17. The depth of the recessed gate 30 is deeper than the depth of the source/drain region 13, 15, therefore the effective channel length L can be lengthened. [0008] Referring to FIG. 3, the channel region 17 is located between the trench isolation layers 11a. The source region 13 (FIG. 1) and the drain region 15 (FIG. 1) are located at the front and the back of the channel region 17 respectively, and the recessed gate 30 is located on the channel region 17. As shown in the drawing, the recessed gate 30 has a positive slopped sidewall and the trench isolation layers 11a also have a positive slopped sidewall. As a result, as shown in FIG. 3, the above structure creates a sharp tip 17a in the channel region 17 at which the recessed gate 30 and the trench isolation layer 11a adjoin each other. Referring to FIG. 1, the sharp tip 17a is formed along the boundary between the channel region 17 and the trench isolation layer 11a. As a result, when such a MOS transistor works, a channel is formed not only under the recessed gate 30, and but also in the sharp tip 17a. The channel formed in the sharp tip 17a can reduce the effective channel length of the MOS transistor with the recessed gate 30. Therefore, the MOS transistor with the recessed gate may result in a failure to suppress the short channel effect. SUMMARY OF THE INVENTION [0009] Exemplary embodiments of the present invention provide a MOS transistor with a recessed gate structured for suppressing the reduction of effective channel length. The present invention also provides a method of fabricating a MOS transistor with a recessed gate structured to suppress the reduction of effective channel length. [0010] According to one embodiment, the present invention provides a MOS transistor which includes a semiconductor substrate, and a trench isolation layer located in a predetermined region of the semiconductor substrate for defining an active region. The trench isolation layer has a negative slope on at least a lower sidewall thereof. A recessed gate is located in a predetermined region of the active region, and a bottom surface of the recessed gate is placed adjacent or contacts the negatively slopped sidewall of the trench isolation layer. [0011] The overall sidewall including the lower sidewall of the trench isolation layer may have a negative slope. However, alternatively, the trench isolation layer may have a positive slope on its upper sidewall and a negative slop on the lower sidewall. The trench isolation layer is preferably formed of high-density plasma chemical vapor deposition (HDP-CVD) insulating layer. [0012] A gate insulating layer may be interposed between the recessed gate and the active region and the recessed gate may be formed of polysilicon. [0013] The present invention provides a method of fabricating a MOS transistor. The method comprises first preparing a semiconductor substrate. An isolation trench having a negative slope on at least a lower sidewall is formed in a predetermined region of the semiconductor substrate to define an active region. The isolation trench is filled with an insulating layer, and the semiconductor substrate having the isolation trench filled with the insulating layer is polished by using a CMP so as to form a trench isolation layer. A recessed gate is formed in a predetermined region of the active region, and a bottom surface of the recessed gate is placed adjacent or contacts the negatively slopped lower sidewall of the trench isolation layer. [0014] The isolation trench may be formed so as to have a negative slope on the overall sidewall including the lower sidewall. Alternatively, the isolation trench may be formed to have a positive slope on its upper sidewall and a negative slope on its lower sidewall. [0015] In the process of forming the isolation trench, negative-slope etching may be employed when the sidewall is formed. The negative-slope etching may be performed by a dry etching or a wet etching. The dry etching may be performed by using a substrate etching gas including NF.sub.3 and SF.sub.6. [0016] Before the isolation trench is filled with the insulating layer, a liner is preferably formed inside the isolation trench. The filling of the isolation trench with the insulating layer may include partially filling the isolation trench with a first insulating layer. The first insulating layer is anisotropically etched to form an insulating spacer on the negatively slopped lower sidewall of the isolation trench. The isolation trench having the insulating spacer is substantially completely filled with a second insulating layer. [0017] The first and second insulating layer is can be formed of an HDP-CVD insulating layers. The anisotropically etching of the first insulating layer can be performed by using a reactive ion etching (RIE) process. The insulating spacer can be formed to cover at least the negatively slopped lower sidewall. [0018] In the process of forming the recessed gate, a channel trench may be formed in a predetermined region of the active region such that the bottom surface of the channel trench contacts a negatively slopped lower sidewall of the trench isolation layer. A gate insulating layer is formed on the bottom surface of the channel trench, and a gate conductive layer is formed on the gate insulating layer to fill the channel trench. Then, the gate conductive layer is patterned. Before forming the gate insulating layer, it is preferable to include a process of performing a channel ion implantation process onto the channel trench. The gate conductive layer may be formed of polysilicon. BRIEF DESCRIPTION OF THE DRAWINGS [0019] The above and other features and advantages of the present invention will become more apparent to those of ordinary skill in the art by describing in detail preferred embodiments thereof with reference to the attached drawings in which: [0020] FIG. 1 is a plane view of a typical MOS transistor with a recessed gate; Continue reading about Mos transistor with recessed gate and method of fabricating the same... Full patent description for Mos transistor with recessed gate and method of fabricating the same Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Mos transistor with recessed gate and method of fabricating the same patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. 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