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  Mos circuit arrangementUSPTO Application #: 20060113602Title: Mos circuit arrangement Abstract: A MOS circuit arrangement includes a silicon substrate, a semiconductor device, a field oxide layer, and a poly-protective layer. The silicon substrate has a conductive doping incorporated therein, wherein the semiconductor device is electrically connected with the silicon substrate. The field oxide layer is formed on the silicon substrate at a position spaced apart from the terminal of the semiconductor device to form an active region between the field oxide layer and the semiconductor device. The poly-protective layer deposited on the active region to communicate the field oxide layer with the terminal of the semiconductor device, wherein the poly-protective layer provides a junction breakdown path between the semiconductor device and the silicon substrate to increase a junction breakdown voltage of the semiconductor device. (end of abstract) Agent: Advanced Analog Technology, Inc. - Hsinchu, TW Inventors: Cheng-Yu Fang, Wei-Jung Chen, Sheng-Ti Lee, Chien-Peng Yu, Yi-Cheng Wang USPTO Applicaton #: 20060113602 - Class: 257368000 (USPTO) Related Patent Categories: Active Solid-state Devices (e.g., Transistors, Solid-state Diodes), Field Effect Device, Having Insulated Electrode (e.g., Mosfet, Mos Diode), Insulated Gate Field Effect Transistor In Integrated Circuit The Patent Description & Claims data below is from USPTO Patent Application 20060113602. Brief Patent Description - Full Patent Description - Patent Application Claims
BACKGROUND OF THE PRESENT INVENTION [0001] 1. Field of Invention [0002] The present invention relates to a semiconductor, and more particularly to a Metal Oxides Semiconductor (MOS) circuit arrangement which is capable of increasing a junction breakdown voltage of the relevant semiconductor. [0003] 2. Description of Related Arts [0004] Referring to FIG. 1 of the drawings, a conventional NMOS circuit arrangement is illustrated. Typically, the NMOS circuit arrangement comprises a semiconductor device 10P, such as a sensor or a predetermined combination of such typical semiconductor electronics as MOS transistors, a substrate 20P of a predetermined type, such as a P-well substrate, and a Field Oxide (FOX) Layer 30P which is typically utilized to isolate two of the adjacent semiconductor devices 10P. [0005] During a typical manufacturing process for the NMOS circuit arrangement, a technique known as wet oxidation has been widely utilized for forming the FOX layer 30P, wherein the NMOS circuit arrangement is exposed to oxygen rich environment. However, in that oxygen rich environment which forms the FOX layer 30P, there usually exist lateral diffusions between oxygen and the liquid molecules which may eventually produce a tapering oxide layer formed on the semiconductor device 10P. This layer of tapering oxide is generally known as bird's bead which, due to residual stress developed therewithin during the oxidation process, is likely to contain defective or spontaneously damaged structure. This random defective structure--which is generally called "punch-through" effect among those skilled in the art, inevitably affects the overall performance of the entire MOS circuit arrangement and decreases the life-span of the utility application in which this MOS circuit arrangement implements. As a matter of conventional art, the possibility of punch-through occurring is particularly high in very small scale transistors, because a lower impurity concentration usually occurs in the vicinity of the source and drain depletion regions of the relevant transistors. [0006] As a result, methods of preventing this "punch through" problem have frequently been developed. For example, considerable efforts have been devoted to increase the impurity concentration in the vicinity of the source and drain depletion regions of the relevant semiconductors. A typical impurity is boron which is applied to P-field implant wherein a particularly high concentration of this impurity is usually applied in the vicinity of semiconductor device 10P--FOX layer 30 junction. However, while this type of methods is theoretically possible, it is difficult to achieve a consistent and reliable performance of the increased breakdown voltage since in a sophisticated MOS circuit arrangement, each different semiconductor has different electrical characteristics, therefore an invariable increase in boron concentration for all semiconductors may render some of them improperly operating and, as a result, ultimately affecting the overall performance of the entire MOS circuit arrangement. [0007] Similarly, for conventional PMOS circuit arrangement, a higher concentration of phosphorous is usually applied at the silicon semiconductor device 10--FOX 30 junction to increase breakdown voltage. Here, the problems are similar to that of the NMOS. [0008] Thus one is facing a tension of punch through problem and breakdown voltage problem. The conventional arts are less than satisfactory in striking a well balance, not to mention resolving both problems at all. [0009] On the other hand, referring to FIG. 2 of the drawings, a typical path of an Integrated Circuit (IC), such as a MOS circuit arrangement, is illustrated. Conventionally, MOS technology, especially submicron CMOS IC, is extremely vulnerable to electrostatic discharge (ESD) the existence of which is due to a wide range of reasons. As a result, there exist some sorts of ESD protection circuit which are aimed for blocking ESD from reaching the relevant semiconductors. [0010] A main disadvantage of these ESD protection circuits is that they usually take up considerable amount of circuit area. In an information era in which everyone is pursuing smaller and smaller electronics equipments, these ESD protection circuits present a major barrier for further reducing the physical size of MOS circuit arrangement and therefore indirectly prevent electronic equipments from being further decreased in size. [0011] Thus, ESD protection circuits, while electronically feasible for blocking ESD within a semiconductor IC, is regrettably not ideal for practical purpose, and even rapidly obsolete in an era which requires smaller and faster electronic devices. SUMMARY OF THE PRESENT INVENTION [0012] A main object of the present invention is to provide a MOS circuit arrangement which is capable of increasing a junction breakdown voltage of a semiconductor device while at the same time prevent punch-through effect thereof. [0013] Another object of the present invention is to provide a MOS circuit arrangement which comprising a poly-protective layer which substitutes conventional space-occupying ESD circuit for blocking ESD within the MOS circuit arrangement, thus significantly reducing a physical size of the present invention, or the equipment in which the present invention is incorporated. [0014] Another object of the present invention is to provide a MOS circuit arrangement which does not involves complicated circuits for increasing breakdown voltage as well as minimizing punch-though problem. Thus, the present invention can be manufactured with minimum cost and therefore enjoying low ultimate selling price of consumers. [0015] Another object of the present invention is to provide a MOS circuit arrangement which may be embodied as either a NMOS circuit arrangement or a PMOS circuit arrangement so as to maximize compatibility of the present invention to a wide variety of MOS circuits and applications. [0016] Accordingly, in order to accomplish the above objects, the present invention provides a Metal Oxide Semiconductor (MOS) circuit arrangement, comprising: [0017] a silicon substrate having a conductive doping incorporated therein; [0018] a semiconductor device, having a terminal, electrically connected with the silicon substrate; [0019] a field oxide layer formed on the silicon substrate at a position spaced apart from the terminal of the semiconductor device to form an active region between the field oxide layer and the semiconductor device; and [0020] a poly-protective layer deposited on the active region to communicate the field oxide layer with the terminal of the semiconductor device, wherein the poly-protective layer provides a junction breakdown path between the semiconductor device and the silicon substrate to increase a junction breakdown voltage of the semiconductor device. [0021] These and other objectives, features, and advantages of the present invention will become apparent from the following detailed description, the accompanying drawings, and the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS Continue reading... Full patent description for Mos circuit arrangement Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Mos circuit arrangement patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. 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