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Modified facet etch to prevent blown gate oxide and increase etch chamber lifeRelated Patent Categories: Active Solid-state Devices (e.g., Transistors, Solid-state Diodes), Integrated Circuit Structure With Electrically Isolated ComponentsModified facet etch to prevent blown gate oxide and increase etch chamber life description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20070278611, Modified facet etch to prevent blown gate oxide and increase etch chamber life. Brief Patent Description - Full Patent Description - Patent Application Claims
CROSS-REFERENCE TO RELATED U.S. PATENT APPLICATIONS [0001] This application is a Divisional of U.S. application Ser. No. 10/887,049 filed Jul. 8, 2004, now U.S. Pat. No. 7,262,136, issued Aug. 28, 2007, which is a Continuation of U.S. application Ser. No. 09/854,975 filed May 14, 2001, now U.S. Pat. No. 6,762,125, issued Jul. 13, 2004, all applications hereby incorporated herein by reference. FIELD OF THE INVENTION [0002] This invention relates to semiconductor manufacture, and more particularly to facet etching useful for improving subsequent dielectric layer step coverage. BACKGROUND OF THE INVENTION [0003] A major goal of any dielectric deposition system is good step coverage. Step coverage refers to the ability of subsequent layers to evenly cover layers ("steps") already present on the substrate. Facet etches are frequently used to provide superior step coverage. The standard facet etch uses a high energy argon ion which physically bombards the material being etched and thereby etches the oxide at an angle to allow subsequent material to have the best step coverage possible. However, if the argon ions etch through the oxide and reach metal or another conductor, they disperse their energy into the metal line or other conductor. This energy finds its way to a ground through a weak spot in the gate oxide thereby resulting in a blown gate. [0004] In sputter etching, ions which impinge on horizontal surfaces have a minimal effect on etch rate and profile. However, the sputter yield of the etch at the corners is approximately four times that of the etch rate of a horizontal surface, thereby creating an extreme etch profile. The effect is the wearing away of the corners of a feature at approximately 45 degree angles. The material removed by the sputter etch is redeposited along the sides of the feature and along the surface of the substrate. [0005] An issue associated with sputter etching is that some of the sputtered material redeposits frequently on the inside surfaces of the etching chamber. This redeposited material must be removed at intervals, thereby taking the etching chamber off-line. SUMMARY OF THE INVENTION [0006] The process of the present invention employs a two-step etching sequence wherein an insulating layer deposited on top of a plurality of conductive structures is first etched by a high energy inert gas ion to physically sputter the oxide material and form a faceted etch. The first step etch is terminated prior to reaching a predetermined target depth. The second step etch is conducted with a reactant gas to further remove the insulating material down to the target depth. [0007] In a preferred embodiment, the method of the invention comprises forming a first layer comprising an insulating material superjacent a substrate comprising a plurality of conductive structures, at least some of the conductive structures being placed apart to form spaces between the conductive structures, such that the first layer forms in at least some of the spaces between the conductive structures and the first layer is formed to a thickness at least equal to the target depth. Next, the first layer is etched by directing a plasma of an inert gas at the first layer formed in at least some of the spaces between the conductive structures. The plasma is of sufficient energy to sputter material from the first layer thereby forming a facet etch in the first layer formed in the spaces between the conductive structures. The first etch is terminated when the first layer has been etched to a predetermined depth which is less than the target depth. Next, the first layer is etched, in a second etch, by contacting the first layer with a reactive chemical gas/plasma. The second etch is terminated when the first layer has been etched to the target depth. [0008] Various other features, objects and advantages of the present invention will be made apparent from the following detailed description and the drawings. BRIEF DESCRIPTION OF THE DRAWINGS [0009] Preferred embodiments of the invention are described below with reference to the following accompanying drawings, which are for illustrative purposes only. Throughout the following views, reference numerals will be used in the drawings, and the same reference numerals will be used throughout the several views and in the description to indicate same or like parts. [0010] FIG. 1 is a schematic view of a semiconductor device having a plurality of conductive structures. [0011] FIG. 2 is a schematic view of the semiconductor device of FIG. 1 at a later stage in the process. [0012] FIG. 3 shows a schematic view of a portion of the semiconductor device of FIG. 2. [0013] FIG. 4 shows the semiconductor device of FIG. 2 at a later stage in the process. [0014] FIG. 5 shows a portion of the semiconductor device of FIG. 4. [0015] FIG. 6 shows the semiconductor device of FIG. 4 at a later stage of the process. DETAILED DESCRIPTION OF THE INVENTION [0016] In the following detailed description, references made to the accompanying drawings which form a part hereof and in which is shown by way of illustration specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention, and it is to be understood that other embodiments may be utilized and that structural, logical and electrical changes may be made without departing from the spirit and scope of the present invention. [0017] FIG. 1 shows a semiconductor device 1 suitable for use in a preferred embodiment of this invention. The semiconductor device I comprises a plurality of conductive structures 12 overlying a substrate 10. The conductive structures 12 are positioned in close proximity to each other to form spaces 14 between the conductive structures 12. [0018] Conductive structures 12 can be any conductive element of semiconductor device 1 but are typically metal lines, runners, leads or interconnects. Conductive structures 12 typically comprise at least one of titanium, tungsten, tantalum, molybdenum, aluminum, copper, gold, silver, nitrides thereof and silicides thereof. Continue reading about Modified facet etch to prevent blown gate oxide and increase etch chamber life... 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