Miscellaneous active electrical nonlinear devices, circuits, and systems inventions 08/08

20080204083 - Voltage comparator: P

20080204084 - Low heat dissipation i/o module using direct drive buck converter: A current-loop output circuit for an industrial controller provides for low power dissipation and reduced part count by driving current loads of different resistances directly from a switched voltage source. Proper filtering and design of a feedback loop allows the necessary transient response times to be obtained.... Agent: Rockwell Automation, Inc./bf

20080204085 - Photodetector: An I/F converter 10 contained in a photodetector is provided with a first comparing portion 111, a second comparing portion 112, a current mirror circuit 14, an SR type flip-flop circuit 16, a buffer amplifier 18, a first capacitor C1, a second capacitor C2, a switch SW1, a switch SW2,... Agent: Drinker Biddle & Reath (dc)

20080204086 - Apparatus for driving source lines and display apparatus having the same: An apparatus for driving source lines includes an output buffer, a first switch and a second switch. The output buffer outputs a first voltage and a second voltage having an opposite phase to the first voltage during an output interval including a first interval portion and a second interval portion.... Agent: F. Chau & Associates, LLC

20080204087 - Method and circuit arrangement configured for driving a field-effect-controlled transistor: A method and circuit arrangement including driving a field effect controlled transistor. One embodiment provides a first load terminal, a second load terminal and a control terminal. The control terminal is driven, at least during a Miller plateau phase of the transistor, with a pulse-width-modulated control signal whose period duration... Agent: Dicke, Billig & Czaja

20080204088 - High-speed divider with reduced power consumption: A method for dividing a signal having a first frequency by a divide ratio includes selecting, based on the divide ratio, a first pulse width of at least one signal having a second frequency and being generated by at least a corresponding one of a plurality of pulse-width control circuits... Agent: Zagorin O'brien Graham LLP

20080204089 - Dynamic frequency dividing circuit operating within limited frequency range: A frequency dividing circuit has a master circuit and a slave circuit, and a load section in at least either one of the master and slave circuits is constructed to provide an impedance that decreases with increasing frequency.... Agent: Arent Fox LLP

20080204090 - Glitch-free clock regeneration circuit: A clock regeneration circuit and method including an asynchronous clock signal input to a meta-stability filtering circuit, a synchronous clock signal input to the meta-stability filtering circuit with a frequency lower than the asynchronous clock signal, and being over-sampled and rate adapted to the asynchronous clock signal, an edge detector... Agent: Kramer & Amado, P.C.

20080204091 - Semiconductor chip package and method for fabricating semiconductor chip: A semiconductor chip package and a semiconductor chip fabricating method are provided. A semiconductor chip package comprises at least two semiconductor chips having a stacked configuration, the semiconductor chips at least one of: sharing DC signals of DC generating circuits provided by one of the semiconductor chips; and sharing a... Agent: Mills & Onello LLP

20080204092 - Cicuit arrangement, in particular phase-locked loop, as well as corresponding method: In order to further develop a circuit arrangement (100), in particular to a phase-locked loop for sub-clock or sub-pixel accurate phase-measurement and phase-generation, as well as a corresponding method in such way that no clock multiplier phase-locked loop is to be provided behind the time-to-digital converter and that neither an... Agent: Nxp, B.v. Nxp Intellectual Property Department

20080204095 - Method and apparatus for controlling power-down mode of delay locked loop: A method and apparatus for controlling a power-down mode of a delay locked loop (DLL), in which the apparatus includes a first switch unit, a DLL, and a second switch unit. The first switch unit transfers a first clock signal in response to a clock input enable signal. The DLL... Agent: F. Chau & Associates, LLC

20080204093 - Multiphase generator with duty-cycle correction using dual-edge phase detection and method for generating a multiphase signal: Embodiments of a multiphase generator with duty-cycle correction are generally described herein. In some embodiments, the multiphase generator comprises controllable delay stages arranged in series and dual-edge phase detector circuitry. The dual-edge phase detector circuitry may generate a control signal to adjust the delay provided by the delay stages based... Agent: Schwegman, Lundberg & Woessner, P.A.

20080204094 - Semiconductor memory device and method for driving the same: The present invention intends to provide a semiconductor memory device including a delay locked loop (DLL) circuit capable of generating a duty-corrected delay locked clock. A semiconductor memory device includes: a DLL circuit for generating a delay locked clock through a delay locked operation; and a duty-correction circuit for correcting... Agent: Blakely Sokoloff Taylor & Zafman LLP

20080204096 - Circuit and method to convert a single ended signal to duplicated signals: A circuit to convert a single ended signal to differential signals is disclosed. The circuit has two paths with each of the two paths comprising a plurality of stages. The number of stages in each of the two paths is the same. A first path of the two paths includes... Agent: Slater & Matsil LLP

20080204099 - Clock generator and clock duty cycle correction method: A clock duty cycle correction (DCC) circuit for correcting a clock duty cycle of an external clock includes a phase comparator for comparing a phase of a rising clock with that of a falling clock to thereby output comparing signal; a DCC controller for outputting a DCC enable signal and... Agent: Blakely Sokoloff Taylor & Zafman LLP

20080204098 - Current sharing for multiphase power conversion: Current sharing scheme based on input power and/or the power efficiency for a power stage with multiple phases and/or paralleled modules is described. According to the scheme, duty cycles of different phases/modules may be adaptively adjusted until the minimum input power and/or the maximum power efficiency is achieved. For certain... Agent: Intel Corporation C/o Intellevate, LLC

20080204097 - Inverter based duty cycle correction apparatuses and systems: Apparatuses, circuits, and methods to reduce duty cycle errors are disclosed. Embodiments generally comprise buffer circuits coupled with error detection circuits and correction feedback circuits that sense duty cycles errors in output signals from the buffer circuits, generate error signals, and couple the error signals back to the inputs to... Agent: Schubert, Osterrieder & Nickelson, PLLC C/o Intellevate, LLC

20080204100 - Logic circuit: For example, a gain control part and a common node control part are provided in a logic circuit including a data acquisition part that has a differential amplifier configuration and acquires a data input signal when a click signal is an “H” level and a latch part that latches a... Agent: Stanley P. Fisher Reed Smith LLP

20080204101 - Hysteresis characteristic input circuit including resistors capable of suppressing penetration current: In a hysteresis characteristic input circuit, first and second resistors are connected in parallel between a first power supply terminal and a connection point, and first and second MOS transistors are connected in parallel between the connection point and a second power supply terminal and are controlled by an input... Agent: Mcginn Intellectual Property Law Group, PLLC

20080204102 - Method to regulate propagation delay of capacitively coupled parallel lines: Capacitive coupling between adjacent parallel lines in an integrated circuit is made more uniform and allows for better timing control of the lines through the use of inverters placed on one or both of the adjacent interconnect lines. By staggering the placement of inverters along adjacent lines, constructive and destructive... Agent: Hogan & Hartson LLP

20080204103 - Clock skew controller and integrated circuit including the same: A clock skew controller for adjusting a skew between a first clock, which is input to a first clock mesh, and a second clock mesh input to a second clock mesh, includes a pulse generator adapted to output a pulse signal corresponding to a delay time between a first output... Agent: Lee & Morse, P.C.

20080204104 - Clocking architecture in stacked and bonded dice: A method and apparatus for distributing clock signals throughout an integrated circuit is provided. An embodiment comprises a distribution die which contains either the clock signal distribution network by itself, or the clock signal distribution network in tandem with a clock signal generator. The distribution die is electrically connected through... Agent: Slater & Matsil, L.L.P.

20080204105 - Power supply device, signal output apparatus and power supply method: A power supply device capable of suitably reducing a loss even in a case where power is supplied to an output device which outputs a high-frequency signal, a signal output apparatus in which a loss is suitably reduced, and a power supply method capable of suitably reducing a loss. The... Agent: Staas & Halsey LLP

20080204106 - Signal adjustment techniques: An apparatus includes a filter module, an amplification module, and an adjustment signal source. The filter module generates a filtered signal based on a received signal. This filtered signal has a level shift corresponding to a difference between a direct current (DC) level of the filtered signal and a DC... Agent: Tyco Electronics Corporation

20080204108 - De-emphasis system and method for coupling digital signals through capacitively loaded lines: A system for de-emphasizing digital signals, such as address signals, boosts the level of the signals for one clock period prior to transmitting the signals through signal lines that may have a relatively large capacitance. The system may include a delay circuit that delays the digital signal for a period... Agent: Edward W. Bulchis, Esq. Dorsey & Whitney LLP

20080204107 - Mos resistance controlling device and mos attenuator: A MOS resistance controlling device includes: a plurality of MOS transistors having a first MOS transistor to N-th (the integer N is larger than 1) MOS transistor being serially connected, the source of the first MOS transistor being set to a first reference potential, the drain the N-th MOS transistor... Agent: Amin, Turocy & Calvin, LLP

20080204111 - High-impedance level-shifting amplifier capable of handling input signals with a voltage magnitude that exceeds a supply voltage: A level-shifting amplifier is provided for level-shifting an input signal with a voltage magnitude that exceeds a supply voltage of the amplifier. In operation, the amplifier has an input impedance of greater than 100 MOhms.... Agent: Zilka-kotab, PC

20080204109 - High-performance level shifter: A level shifter is presented that allows fast switching while requiring low power. In accordance with some embodiments of the invention, the level shifter is a two stage level shifting circuit with p-channel and n-channel transistors biased so as to limit the potential between the source to gate or drain... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080204110 - Level shift circuit: A level shift circuit for converting a first signal level into a second signal level, includes a load circuit connected to the second power supply voltage, a first high voltage-resistant transistor in which a drain is connected to the load circuit, and a predetermined constant voltage is applied to a... Agent: Arent Fox LLP

20080204112 - Moca-compliant multiplexing device: A multiplexing device complies with Multimedia over Coax Alliance (MoCA) specifications, and includes a circuit board disposed in a casing, first and second adapters disposed on the circuit board and adapted to be connected between an input end and an output end, and a shielding component. The first adapter includes... Agent: Ladas & Parry LLP

20080204113 - Ultra fine pitch i/o design for microchips: A microchip includes at least one I/O area surrounding at least one core circuit area. The I/O area further includes a first I/O cell having at least one first post-driver device connected to a first I/O pad; a second I/O cell having at least one second post-driver device connected to... Agent: L. Howard Chen Kirkpatrick & Lockhart Preston Gates Ellis, LLP

20080204114 - Transmission gate switch, system using the same, and data input/output method thereof: A transmission gate switch includes a switching unit to conduct a switching operation between first and second nodes in response to a switching signal, and an isolation unit to prevent the switching unit from being turned on by a negative swing of the first or second node while the switching... Agent: Stanzione & Kim, LLP

20080204115 - Semiconductor device and method of producing the same, and power conversion apparatus incorporating this semiconductor device: The temperature of a bipolar semiconductor element using a wide-gap semiconductor is raised using heating means, such as a heater, to obtain a power semiconductor device being large in controllable current and low in loss. The temperature is set at a temperature higher than the temperature at which the decrement... Agent: Sheridan Ross PC

20080204117 - Electrical circuit arrangement: The invention relates to an electrical circuit arrangement for generating signal events for initiating or carrying out switching, adjusting or releasing processes. According to the first invention aspect, the inventive electric circuit arrangement comprises an input component for carrying out a selection process for generating an input event and a... Agent: Katten Muchin Rosenman LLP

20080204118 - Inductive proximity switch based on a transformer coupling factor principle: The invention relates to a preferably ferriteless inductive proximity switch having at least one transmitting coil, one oscillator circuit and at least two receiving coils arranged in the alternating magnetic field of the transmitting coil, whereby the transmitting coil and the receiving coil are arranged adjacent to each other on... Agent: Horst M. Kasper Patent Attorney

20080204116 - Sensing apparatus and method: There is described a sensor for sensing the parameter, the sensor comprising a transmit aerial, an intermediate coupling element, a receive aerial electromagnetically coupled to the transmit aerial via the intermediate coupling element, a signal generator operable to generate a periodic excitation signal at a first frequency, and arranged to... Agent: Patent Docket Administrator Lowenstein Sandler PC

20080204119 - Device providing trim values: Devices comprising trimmable electric units and methods for providing trim values to electric units are presented herein. One such device comprises a trimmable electric unit, at least one fuse to provide at least one first trim value, and a trim value provision unit to provide at least one second trim... Agent: Lee & Hayes, PLLC

20080204120 - Pin number reduction circuit and methodology for mixed-signal ic, memory ic, and soc: One amplifier with a PMOS transistor and one resistor string provides a higher pseudo power supply, and the other amplifier with an NMOS transistor and the other resistor string provides a lower pseudo power supply so that a digital functional section is coupled between these pseudo power supplies. Furthermore, the... Agent: Kieun Park Dba Ana Semiconductor

20080204121 - Voltage generating circuit having charge pump and liquid crystal display using same: An exemplary voltage generating circuit (34) includes a first pulse generator (341) configured to provide a first pulse signal having a fixed duty ratio, a second pulse generator (342) configured to provide a second pulse signal having a variable duty ratio, and a charge pump (343) electrically coupled to the... Agent: Wei Te Chung Foxconn International, Inc.

20080204122 - Circuit for eliminating pop sounds at power on and off by a moderate waveform: A circuit for eliminating pop sounds at power on and off by a moderate waveform, which includes a switch, a feedback network, an operational amplifier and an output network. When power-on, a first input terminal of the switch is connected to a low voltage, and an output terminal of the... Agent: Bacon & Thomas, PLLC

20080204123 - Semiconductor device: A semiconductor device includes a P-substrate, an N-well disposed in the P-substrate, an NMOS transistor disposed in the P-substrate and having one of a source and a drain connected to a ground voltage, a P-tap disposed in the P-substrate and connected to a low voltage so as to provide the... Agent: Oliff & Berridge, PLC

20080204124 - Fine-grained power management of synchronous and asynchronous datapath circuits: A power management circuit is provided for controlling power dissipation in at least one combinational logic circuit. The power management circuit includes a detector operative to receive at least a first input signal to the combinational logic circuit and to detect a transition of the first input signal between a... Agent: Ryan, Mason & Lewis, LLP

20080204125 - Internal voltage generator: An internal voltage generator is disclosed. The internal voltage generator may include a comparator for controlling a voltage of a first node in response to a voltage difference between a reference voltage and an internal voltage, an internal voltage driving portion connected between a driving node and an internal voltage... Agent: Harness, Dickey & Pierce, P.L.C

20080204126 - Common mode noise reduction using parasitic capacitance cancellation: A negative capacitance is developed by configuring an inductor as two inversely or opposingly coupled windings having different numbers of turns and connecting a capacitance to a center tap between the two windings. The negative capacitance is developed on the side of the inductor having the winding with the greater... Agent: Whitham, Curtis & Christofferson & Cook, P.C.

20080204127 - Method for ultimate noise isolation in high-speed digital systems on packages and printed circuit boards (pcbs): Improved noise isolation for high-speed digital systems on packages and printed circuit boards is provided by the use of mixed alternating impedance electromagnetic bandgap (AI-EBG) structures and a power island configured to provide ultimate noise isolation. A power island is surrounded by a plurality of mixed AI-EBG structures to provide... Agent: Ibm Corp (ya) C/o Yee & Associates PC

20080204128 - Circuit arrangement with interference protection: A circuit arrangement with an interference protection is disclosed, including a supply line and a ground line, a first circuit and a second circuit. Each of the first and second circuit is connected to the supply line and to the ground line. The circuit arrangement also includes a blocking device... Agent: Eschweiler & Associates LLC

20080204129 - Simplified sallen-key low-pass filter circuit: The Sallen-Key low-pass filter circuit comprises a first resistor (16) and a second resistor (18) connected in series, the first resistor (16) being connected between the second resistor and an input of the circuit. The second resistor (18) is directly connected between the first resistor and an output of the... Agent: Nxp, B.v. Nxp Intellectual Property Department

20080204130 - Oscillator bias injector: A oscillator bias injector system for use in maritime applications in connection with a VSAT communication system including a satellite modem connected to a commercially available high power block upconverter and low noise block downconverter which are both connected to an outdoor antenna mounted on a stabilized platform, which antenna... Agent: James G. Coplit

20080197885 - Circuit for detecting maximal frequency of pulse frequency modulation and method thereof: The circuit for detecting the maximal frequency of the pulse frequency modulation includes an oscillator-controlling unit, a delay circuit and a master-slave register. The oscillator-controlling unit is connected to an oscillator, which generates the pulse frequency modulation signals, and includes a first-half pulse-generating module and a second-half pulse-generating module. The... Agent: Oliff & Berridge, PLC

20080197886 - Circuit for discriminating output of squelch circuit and circuit for regulating sensivity of the same: A circuit for discriminating a ‘Noisy’ state of an output of a squelch circuit is disclosed. A circuit for resolve the ‘Noisy’ state of the output of the squelch circuit is also disclosed which uses the output identification circuit. The output of the squelch circuit and a clear signal are... Agent: Amin, Turocy & Calvin, LLP

20080197887 - Comparator circuit: Provided is a comparator circuit that is capable of operating at high speed and canceling an offset voltage with high precision. The comparator circuit includes a second amplifier circuit for amplifying an output of an amplifier circuit and feeding back the amplified output to an input of the amplifier circuit.... Agent: Brinks Hofer Gilson & Lione

20080197888 - Low voltage shutdown circuit: A low voltage shutdown circuit comprises an input node for receiving a voltage Vin to be monitored, first and second voltage-to-current (V to I) converters arranged to receive Vin at respective inputs and to convert Vin to currents I1 and I2 at respective outputs, and a current comparison circuit arranged... Agent: Koppel, Patrick & Heybl

20080197889 - Semiconductor integrated circuit device and mobile device using same: An IC includes an internal circuit that switches between on-state and off-state in response to an external signal and also includes an oscillator circuit that is externally synchronized. The IC further includes a state holding circuit that, when pulses for synchronizing the oscillator circuit are inputted to a standby pulse... Agent: Fish & Richardson P.C.

20080197890 - Light receiving circuit: A light receiving circuit according to the present invention includes a current control voltage generation circuit 10 outputting control voltages Vcont1 and Vcont2, a first current adjusting circuit 11 generating a first output current Io1 by regulating a first input current Ii1 depending on a voltage difference of the control... Agent: Mcginn Intellectual Property Law Group, PLLC

20080197891 - Frequency synthesizer using two phase locked loops: The application discloses system and method embodiments related to a frequency synthesizer. Embodiments of a frequency synthesizer can have a low phase noise and a narrow channel spacing. Embodiments of a frequency synthesizer can use two phase locked loops. One embodiment of a frequency synthesizer can include a reference frequency... Agent: Rene A. Vazquez

20080197892 - Buffer circuit and control method thereof: The present disclosure has been worked out to provide a buffer circuit and a control method thereof capable of controlling the timing at which the output switching element is changed from an OFF state to an ON state, and preventing the output characteristic from becoming unstable. The buffer circuit includes:... Agent: Arent Fox LLP

20080197893 - Variable off-chip drive: A driver circuit includes a set of selectable drivers each having an individual drive capability, the drivers being selectable such that i) when a subset of the drivers is selected, a signal will be driven by the drivers at a first drive level, and ii) when the subset of the... Agent: Foley & Lardner LLP

20080197894 - Injection locked frequency divider: An injection locked frequency divider includes a signal injection unit, a Hartley voltage controlled oscillator and a biasing unit. The signal injection unit and the biasing unit output an injection signal to the Hartley voltage controlled oscillator to bias the Hartley voltage controlled oscillator. The Hartley voltage controlled oscillator, which... Agent: Bacon & Thomas, PLLC

20080197895 - System and method for power on reset and under voltage lockout schemes: A system and method for power-on reset and under-voltage lockout schemes. The system includes a first transistor, which includes a first gate, a first terminal, and a second terminal, the second terminal being biased to a predetermined voltage. The system includes a second transistor, which include a second gate, a... Agent: Jones Day

20080197896 - Device and method for phase synchronization with the aid of a microcontroller: The phase controller device according to the invention comprises a hardware core that is formed by a signal detector, a voltage-controlled oscillator, a phase comparator, and an integration unit, where the hardware core, by controlling the working clock pulse frequency of the microcontroller, brings an output clock pulse signal that... Agent: Woodcock Washburn LLP

20080197898 - Charge pump regulator and method of producing a regulated voltage: A charge pump regulator has a charge pump to establish a charge path and a discharge path alternately, so as to produce a regulated voltage on an output terminal. The charge pump has at least a current control element on the charge path or the discharge path to control the... Agent: Rosenberg, Klein & Lee

20080197897 - Pll circuit and wireless device: A PLL circuit according to the present invention includes: a voltage controlled oscillator 10; a frequency divider 30 that divides an oscillation signal of the voltage controlled oscillator 10 and outputs a divided oscillation signal; a first phase comparator 40 that outputs a phase difference between the divided oscillation signal... Agent: Hamre, Schumann, Mueller & Larson P.C.

20080197899 - Trimmable delay locked loop circuitry with improved initialization characteristics: Disclosed herein is improved delay locked loop (DLL) initialization circuitry that alters the measurement used to initialize the variable delay line's delay (e.g., entry point or exit point) by using three clock phases: the DLL reference clock (input to the delay line), the reference clock as trimmed by a delay... Agent: Wong, Cabello, Lutsch, Rutherford & Brucculeri, L.L.P.

20080197900 - Delay locked loop for controlling delay time using shifter and adder and clock delaying method: A delay locked loop that controls a delay time period by using a shifter and an adder includes a master delay locked loop and a slave delay locked loop. The master delay locked loop outputs a first digital value corresponding to one clock cycle of a first input clock signal.... Agent: F. Chau & Associates, LLC

20080197903 - Clock pulse duty cycle control circuit for a clock fanout chip: A clock pulse duty cycle control circuit for receiving an input clock signal and for providing an output clock signal having a desired duty cycle. An error signal generator includes a differential integrator that is connected to receive the output clock signal. The differential integrator integrates the output clock signal... Agent: Faegre & Benson Attn: Patent Docketing

20080197902 - Method and apparatus to reduce pwm voltage distortion in electric drives: Methods and apparatus are provided for reducing voltage distortion effects at low speed operation in electric drives. The method comprises receiving a first signal having a duty cycle with a range between minimum and maximum achievable duty cycles, producing a second duty cycle based on the minimum achievable duty cycle... Agent: General Motors Corporation Legal Staff

20080197901 - Multiple pulse width modulation: A method of generating a MPWM signal for a portable device such as a cellular telephone. For a first duty cycle that includes a MPWM frequency having N magnitude levels, the method generates a first waveform comprising a first and a second On pulse during a first MPWM frequency period.... Agent: Womble Carlyle Sandridge & Rice, PLLC

20080197904 - Circuit arrangement for switching a load: A circuit arrangement for switching a load includes at least one at least partially inductive load, at least one high side switch with a controlled path connected in series with the load and between supply terminals for a supply voltage. At least one freewheeling diode is connected with a first... Agent: Lerner Greenberg Stemer LLP

20080197905 - Field-programmable gate array low voltage differential signaling driver utilizing two complimentary output buffers: A low voltage signaling differential signaling driver comprising a first output line coupled to a delay circuit, a first multiplexer and a first output buffer. The first output line is also coupled to an inverter, a second multiplexer and a second output buffer.... Agent: Lewis And Roca LLP

20080197907 - Driver amplifier circuit: A driver amplifier circuit is provided which includes a voltage level shifting circuit and an Op-Amp. A positive power supply terminal and a negative power supply terminal of the Op-Amp receive a first reference voltage and a second reference voltage outputted from the voltage level shifting circuit, causing a DC... Agent: Joe Mckinney Muncy

20080197906 - Reference clock receiver compliant with lvpecl, lvds and pci-express supporting both ac coupling and dc coupling: A reference clock receiver structure according to the invention is provided. The structure preferably includes an input buffer that is formed from a PMOS differentiated pair of transistors and a first supply voltage. The PMOS differential pair receives a pair of differential inputs, and produces a pair of differential outputs.... Agent: Ropes & Gray LLP

20080197908 - Cascode power switch for use in a high-frequency power mesfet buck switching power supply: A cascode power switch for use in a MESFET based switching regulator includes a MOSFET in series with a normally-off MESFET. The cascode power switch is typically connected in between a power source and a node Vx. The node Vx is connected to an output node via an inductor and... Agent: Advanced Analogic Technologies

20080197909 - Capacitative proximity switch, and domestic appliance equipped with the same: A capacitive proximity switch has an electrically conductive sensor surface, which is covered by an electrically non-conductive covering plate and which serves as a part of a capacitor with a capacitance that varies with proximity. A household appliance is equipped with a proximity switch of this type. The sensor surface... Agent: Lerner Greenberg Stemer LLP

20080197910 - Input processing circuit and switch input circuit using the same: An input processing circuit implemented on a semiconductor integrated circuit includes an input terminal for receiving an input signal, a first diode coupled between the input terminal and a power line, a second diode coupled between the input terminal and a ground line, a first MOSFET having a gate and... Agent: Posz Law Group, PLC

20080197911 - Circuit with fuse/anti-fuse transistor with selectively damaged gate insulating layer: A semiconductor integrated circuit is disclosed which includes a main transistor and at least one of a fuse transistor or an anti-fuse transistor (“fuse/anti-fuse transistor”). Each transistor type includes an active region formed in a semiconductor substrate, a gate stack comprising a gate insulation layer and a gate electrode sequentially... Agent: Volentine & Whitt PLLC

20080197912 - Circuit arrangement for generating a temperature-compensated voltage or current reference value: A circuit arrangement for generating a temperature-compensated voltage or current reference value (UREF) from a supply voltage (VCC) based on the bandgap principle comprises a PTAT circuit (201) for generating a PTAT signal (I1) proportional to the absolute temperature, a CTAT circuit (202) for generating a CTAT signal (UBE) inversely... Agent: Muncy, Geissler, Olds & Lowe, PLLC

20080197914 - Dynamic leakage control using selective back-biasing: Embodiments of a dynamic leakage control circuit for use with graphics processor circuitry are described. The dynamic leakage control circuit selectively enables back biasing of the transistors comprising the graphics processor circuits during particular modes of operation. The back biasing levels are controlled by two separate power rails. A first... Agent: Courtney Staniford & Gregory LLP

20080197913 - Energy efficient voltage detection circuit and method therefor: A voltage detection circuit has a first MOSFET device having a drain, a gate, and a source terminal. A feedback element is coupled to the drain terminal and the gate terminal of the first MOSFET device. An input voltage is coupled to the gate terminal of the first MOSFET device.... Agent: Weiss & Moy PC

20080197915 - Semiconductor device chip, semiconductor device system, and method: A semiconductor device chip, semiconductor device system, and a method. One embodiment provides a semiconductor device chip including a device for determining whether the semiconductor device chip is to be placed in a current saving operating mode.... Agent: Dicke, Billig & Czaja

20080197917 - Device for filtering a signal and corresponding method: A device for filtering a signal delivered as output from a sensor installed in a motor vehicle includes a comparator (A) offering as output a first logic signal (SA) representative of the positive and negative transitions of the output signal (SM) from the sensor, a clock (G) delivering a signal... Agent: Young & Thompson

20080197918 - Electronic appliance, communication condition setting device, communication condition setting method and computer program: An electronic appliance having a communication function conforming to a wide band wireless communication system is disclosed. The electronic appliance includes: an EMI pattern information storage part configured to store EMI (electromagnetic interference) pattern information unique to the electronic appliance itself or EMI pattern information unique to an electronic appliance... Agent: Sonnenschein Nath & Rosenthal LLP

20080197916 - Low-voltage noise preventing circuit using abrupt metal-insulator transition device: Provided are a low-voltage noise preventing circuit using an abrupt metal-insulator transition (MIT) device which can effectively remove a noise signal with a voltage less than a rated signal voltage. The abrupt MIT device is serially connected to the electrical and/or electronic system to be protected from the noise signal,... Agent: Cantor Colburn, LLP

20080191746 - Automatic static phase error and jitter compensation in pll circuits: An instantaneous phase error detector (IPED) and method includes a first gate configured to logically OR output phase error signals as data to a first latch, and a second gate configured to logically combine the output phase error signals to clock the first latch. A delay element delays to the... Agent: Keusey, Tutunjian & Bitetto, P.c.

20080191747 - Semiconductor intergrated circuit: A semiconductor integrated circuit includes a first power source having a power supply voltage that operates the semiconductor integrated circuit, a voltage comparator that compares the power supply voltage with a reference voltage, and a comparison result recording unit that records a comparison result of the voltage comparator, wherein the... Agent: Arent Fox LLP

20080191748 - Apparatus for supplying overdriving signal: An apparatus for supplying an overdriving signal in a memory apparatus. The apparatus includes: a voltage detecting block that outputs a plurality of detection signals according to the level of an external voltage, and a pulse generator that outputs the overdriving signals having different pulse widths according to the plurality... Agent: Baker & Mckenzie LLP Patent Department

20080191749 - Clock divider with a rational division factor: This disclosure can provide methods, apparatus, and systems for dividing an input clock or master clock by an integer or non-integer divisor and generating one or more balanced, 50% duty cycle, divided that are phase-aligned to the input clock. The non-integer divisors can include half-integers, N/2, e.g. the division can... Agent: Oliff & Berridge, Plc

20080191750 - Digital delay line based frequency synthesizer: A frequency synthesizer is disclosed. The frequency synthesizer includes a period control word generator, a delta-sigma modulator, and a delay line unit. The period control word generator generates a period control word. The delta-sigma modulator receives the period control word and generates a phase selection signal. The delay line unit... Agent: North America Intellectual Property Corporation

20080191751 - Clock modulation circuit for correcting duty ratio and spread spectrum clock generator including the same: A clock modulation circuit includes a modulation block that receives a fixed clock generated from a reference clock and buffers the fixed clock so as to generate a modulated clock. A correction unit is provided in the modulation block to correct the duty ratio of the modulated clock.... Agent: Venable LLP

20080191752 - Method for dividing a high-frequency signal: A method for dividing a high-frequency signal. The method including: generating, from a first clock signal, a second clock signal, the second clock cycle time greater than the first clock cycle time, an off-time of one cycle of the second clock signal being one first clock cycle time less than... Agent: Schmeiser, Olsen & Watts

20080191753 - Methods and systems for locally generating non-integral divided clocks with centralized state machines: A method for locally generating a ratio clock on a chip includes generating a global clock signal having a global clock cycle. A centralized state machine includes a counter going through a complete cycle in response to a non-integer number of global clock cycles, the state machine generating a control... Agent: Cantor Colburn LLP-ibm Poughkeepsie

20080191754 - Phase coherent differtial structures: Phase-coherent differential structures contain a phase-coherent transformer having two pairs of phase-coherent coupled differential inductors.... Agent: Ladas & Parry

20080191755 - Low-noise frequency divider: A frequency divider has an inverting unit and a plurality of switch inverters in series. Each switch inverter comprises two inphase switches and is controlled by a clock. The two inphase switches of each switch inverter are respectively supplied by a first voltage and a second voltage, while any two... Agent: Grossman, Tucker, Perreault & Pfleger, Pllc

20080191756 - Automatic system clock detection system: An Automatic System Clock Detection System (ASCDS) may provide integrated circuits (ICs) with the capability to detect the frequency of an external crystal oscillator or clock source, and adjust the IC's internal PLL accordingly for proper IC operation. The frequency detection and PLL adjustment may be performed without any additional... Agent: Jeffrey C. Hood Meyertons Hood Kivlin Kowert & Goetzel Pc

20080191757 - Delay locked loop circuit with duty cycle correction and method of controlling the same: A delay locked loop block receives external clocks to generate first internal clocks including a reference clock. An internal delay unit delays the first internal clocks to output second internal clocks, which are fed back to the delay locked loop block. The delay locked loop block adjusts delay time of... Agent: Venable LLP

20080191758 - Automatic bias adjustment for phase-locked loop charge pump: A charge pump (140) having a differential current amplifier with a current source (151) that sources output current (155) in response to a first bias point (141), and a current sink (152) that sinks current in response to a second bias point (142) is provided. The charge pump includes a... Agent: Motorola, Inc

20080191761 - Frequency synthesizer and charge pump circuit used therein: There are included a signal generating circuit (8) that generates, based on a comparison signal outputted from a phase comparator (3) and a clock signal outputted from a crystal oscillation circuit (1) and having a shorter pulse width than the comparison signal, a control signal obtained from a logical product... Agent: Connolly Bove Lodge & Hutz LLP

20080191759 - Loop filter and phase-locked loop: A loop filter includes an input terminal, an output terminal, and a control terminal for a selection signal. At least one low pass filter is disposed between that input terminal and that output terminal. The loop filter is adapted to select a configuration out of a first configuration and at... Agent: Eschweiler & Associates Llc

20080191760 - Plls covering wide operating frequency ranges: The present invention provides a method and mechanism for adapting a single phase-locked loop (PLL) for a wider range of frequencies than has been possible with prior art solutions. An analog comparator circuit that senses the output of the charge pump voltage and provides an signal to a control circuit... Agent: Blakely Sokoloff Taylor & Zafman LLP

20080191763 - Clock control circuit and semiconductor integrated circuit using the same: A clock control circuit includes a first signal generation block for outputting a first internal clock signal, which is enabled after delay of a first time from a rising edge of a first input clock signal and has a high level pulse width shorter by a second time than a... Agent: Baker & Mckenzie LLP Patent Department

20080191762 - Digital hold in a phase-locked loop: A technique that is readily implemented in monolithic integrated circuits includes a method including generating an output clock signal during a presence of a reference clock signal based, at least in part, on a digital control value indicating a phase difference between a feedback signal of a PLL and a... Agent: Zagorin O'brien Graham LLP

20080191765 - Broadband multi-phase output delay locked loop circuit utilizing a delay matrix: A broadband multi-phase output delay locked loop (DLL) circuit can be operated in a wide range of frequencies and generate various phases. Unlike conventional voltage control delay lines in which delay cells are connected in series, the DLL circuit utilizes a delay matrix in which a resistant network is used... Agent: Volentine & Whitt Pllc

20080191764 - System and method for generating a delayed clock signal of an input clock signal: A system and method for generating a delayed clock signal of an input clock signal involves selectively delaying the input clock signal to produce the delayed clock signal based on the duty cycle of the input clock signal and the duty cycle of a logic signal derived from a logic... Agent: Kathy Manke Avago Technologies Limited

20080191766 - Method and apparatus for detecting and adjusting characteristics of a signal: Disclosed is a circuit that adjusts a characteristic of a signal transmitted from a transmitter to a receiver over a communication channel (e.g., a wire, a backplane, etc.). The circuit includes a latch that receives the signal at a predetermined point in the circuit and samples a voltage of the... Agent: Weinick & Associates, Llc

20080191767 - Duty cycle correcting circuit and duty cycle correcting method: A duty cycle correcting circuit includes a first duty ratio correcting unit that widens a high-level period of an input clock in response to a detection signal, thereby correcting a duty ratio of the input clock to output a first corrected clock. A second duty ratio correcting unit narrows the... Agent: Venable LLP

20080191768 - Semiconductor integrated circuit device operating in synchronism with clock and method for controlling duty of clock: A semiconductor integrated circuit device includes a processor, a first clock generating section and a control section. The processor core operates in synchronism with a first clock and includes first and second critical paths. The first clock generating section controls a duty of an externally input second clock to generate... Agent: Sprinkle Ip Law Group

20080191769 - Signal transmission circuit, semiconductor device that includes the signal transmission circuit, method for designing the semiconductor circuit device, and cad device: A CAD device according to the embodiments includes means that determines signal transmission time of each signal transmission circuit in an LSI circuit, means that determines an output inversion rate of a flip-flop circuit included in each signal transmission circuit when the flip-flop circuit is exposed to radiation, means that... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080191770 - System and apparatus for aperature time improvement: In particular embodiments, an apparatus includes a first transistor connected at the gate to a first input signal voltage and a second transistor connected at the gate to a second input signal voltage. The apparatus further includes a deactivation element coupled to the transistors, the deactivation element being operable to... Agent: Baker Botts L.l.p.

20080191771 - Data sampling clock edge placement training for high speed gpu-memory interface: Circuits, methods, and apparatus for training a phase shift circuit to provide a phase shift for improved data recovery. A specific embodiment of the present invention provides a variable delay cell. A delay through the variable delay cell is changed while training patterns are received. The presence of errors in... Agent: Townsend And Townsend And Crew LLP

20080191772 - Clock correction circuit and method: The present invention relates to the reduction in errors in the phase of quadrature clock signals and provides a correction circuit for signals which are required to have as close to that precise phase relationship as possible. The arrangement is based upon a circuit which aims to bring signals which... Agent: Texas Instruments Incorporated

20080191773 - Delay apparatus, and delay locked loop circuit and semiconductor memory apparatus using the same: A delay apparatus, and a delay locked loop circuit and a semiconductor memory apparatus using the same are provided. A delay locked loop circuit includes a register controlled delay part that delays a plurality of clocks input during an initial operation by delay amounts among initial delay amounts to be... Agent: Venable LLP

20080191774 - Clock circuit: A clock circuit with a plurality of inputs for a plurality of respective clock signals, the clock signals alternating between a first and a second state. At least one divider circuit is arranged to take an input clock signal and provide an output that is in the first state for... Agent: Texas Instruments Incorporated

20080191775 - Baseline wandering correction device and related method: The invention discloses baseline wandering correction techniques. A baseline wandering correction device comprises a differentiator differentiating a data signal to generate a differentiated signal, a operation signal coupling to the differentiator and proceeding with an operation based on the data signal according to the differentiated signal to generate an operated... Agent: Joe Mckinney Muncy

20080191776 - Signal receiver circuit capable of improving area and power efficiency in semiconductor integrated circuits: A signal receiver circuit includes a first level detector for offset-controlling a first output node in response to a pair of first reference signals. A second level detector offset-controls a second output node in response to a pair of second reference signals.... Agent: Baker & Mckenzie LLP Patent Department

20080191777 - Level shifter capable of high speed operation and high-speed level shifting method: A level shifter capable of high speed operation and a high-speed level shifting method. The level shifter includes a pull-down switching unit configured to selectively connect a first node and a second node with a first power supply (ground) voltage in response to a first switching signal and a (complementary)... Agent: F. Chau & Associates, Llc

20080191778 - Gm/c tuning circuit and filter using the same: A Gm/C tuning circuit. The Gm/C tuning circuit comprises an integrator, a transconductance amplifier, and a switched capacitor circuit. The integrator has a first input terminal, a second input terminal, and an output terminal providing a control voltage. The transconductance amplifier receives the control voltage and a first input voltage... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20080191779 - Circuit and method for determining current in a load: A circuit (1) is described for determining the current (Iload) in a load (6), the circuit having a main transistor (2) and a sense transistor (3), each transistor having a main current path (4, 5) and a control terminal (9, 10), the main current paths each operably connected in parallel... Agent: Nxp, B.v. Nxp Intellectual Property Department

20080191780 - Electronic fuse apparatus and methodology including addressable virtual electronic fuses: A virtual electronic fuse (VEF) apparatus and methodology are disclosed that permit the state of an electronic fuse to change from an un-blown state to a blown state and then back to a virtual un-blown state. In one embodiment, the electronic fuse may change from the virtual un-blown state back... Agent: Mark P. Kahler

20080191781 - Virtual electronic fuse apparatus and methodology: A virtual electronic fuse apparatus and methodology are disclosed that permit the state of an electronic fuse to change from an un-blown state to a blown state and then back to a virtual un-blown state. In one embodiment, the electronic fuse may change from the virtual un-blown state back to... Agent: Mark P. Kahler

20080191782 - Simplified bias circuitry for differential buffer stage with symmetric loads: A biasing circuit for biasing differential delay elements is provided. The circuit is a feedback-free circuit consisting of a CMOS output stage having a P-type transistor and an N-type transistor, with a diode connected transistor between the P-type transistor and the N-type transistor, the output stage receiving the control voltage... Agent: Smart & Biggar P.o. Box 2999, Station D

20080191784 - Ac coupling and gate charge pumping for nmos and pmos device control: An AC electrically coupled FET device (301) is disclosed with a coupling capacitor (302) disposed for receiving a digital input signal having transitions and for AC coupling this input signal to the gate terminal of the FET device (301). A reference bias circuit (306) is provided for providing a first... Agent: Nxp, B.v. Nxp Intellectual Property Department

20080191787 - Charge pump with cascode biasing: In particular embodiments, a charge pump includes a first input transistor operable to receive an up signal and in response to receiving the UP signal, transmit a corresponding output current from a positive power supply to an output node. The charge pump further includes a second input transistor operable to... Agent: Baker Botts L.l.p.

20080191786 - High voltage generation circuit and method for generating high voltage: A high voltage generation circuit includes a delay circuit configured to generate multiple delay clock signals based on a clock signal. The delay clock signals include corresponding different predetermined delay times. The high voltage generation circuit further includes multiple pumps corresponding to the delay clock signals. The pumps are configured... Agent: Volentine & Whitt Pllc

20080191785 - High voltage generation circuit and method for reducing peak current and power noise for a semiconductor memory device: A high voltage generation circuit for use with a semiconductor memory device includes a plurality of high voltage generation units and a control circuit. The high voltage generation units generate high voltages having different voltage levels in response to corresponding clock signals. The control circuit generates clock signals, which do... Agent: Volentine & Whitt Pllc

20080191783 - Symmetric charge pump replica bias detector: A charge pump replica bias detector is disclosed which provides a charge pump with a greater working output voltage range or larger output compliance. A larger working range will provide a charge pump with more symmetric source and sink currents than prior designs with a reduction of the multiple frequency... Agent: Fish & Richardson P.c.

20080191788 - Soi mosfet device with adjustable threshold voltage: An SOI semiconductor device includes a silicon semiconductor layer divided into an FET region with source, channel, and drain regions therein formed on a BOX layer, with a switch region next to the FET region; and a contact region next to the switch region distal from the FET region. The... Agent: International Business Machines Corporation Dept. 18g

20080191789 - Method and apparatus for adjusting a power supply of an integrated circuit: Disclosed is a circuit configured to apply a supply voltage to a switching element (e.g., a transistor). The circuit includes a latch and a processor. The latch is configured to sample a voltage of an output signal of the switching element, and the processor is configured to generate a power... Agent: Weinick & Associates, Llc

20080191791 - Semiconductor integrated circuit device: A semiconductor integrated circuit device includes: a switching current observer for observing a switching current; a leakage current observer for observing a leakage current; a comparator which compares the switching current and the leakage current with each other; a threshold voltage controller for controlling a substrate bias voltage in order... Agent: Dickstein Shapiro LLP

20080191790 - Voltage regulation system: One aspect of the invention relates to a voltage regulation process as well as to a voltage regulation system. A first voltage, present at an input of the voltage regulating system, is changed into a second voltage, which can be tapped at an output of the voltage regulation systems, with... Agent: Dicke, Billig & Czaja

20080191792 - Voltage generating circuit: Disclosed is a voltage generating circuit which steps down a voltage to output a stepped down voltage. The voltage generating circuit includes first and second transistors. The drains of the first and second transistors are connected to a higher voltage power supply. The gate of the first transistor is connected... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20080191793 - Ratioed feedback body voltage bias generator: A current mirror circuit includes a reference current source that generates a reference current, a reference transistor, a mirror transistor and a ratioed body bias feedback unit. The reference transistor has a first node that is coupled to the output of the reference current source, a gate that is coupled... Agent: Ibm Corporation

20080191794 - Method and apparatus for tuning an active filter: A method of tuning an RC time constant includes the steps of providing a predetermined time period value associated with a predetermined RC time constant, providing a DC reference signal, generating an second signal responsive to charging a capacitor until magnitudes of the second signal and the DC reference signal... Agent: Madson & Austin

20080191795 - Method and apparatus for tuning an active filter: A tuning circuit for tuning an active filter includes a resistor-capacitor circuit comprising a variable capacitor and a resistor equivalent to a first resistor and a second resistor serially connected to the first resistor, a voltage generator for providing a constant reference voltage to the first resistor, a current replicating... Agent: Madson & Austin

20080191796 - Calibration apparatus and method for programmable response frequency selecting elements: Disclosed is a calibration apparatus and method for programmable response frequency selecting elements. The calibration apparatus comprises a basic reference source, a programmable counter, a control logic unit, and a frequency to time constant converter. The programmable counter generates plural different frequency signals required by the frequency selecting elements with... Agent: Lin & Associates Intellectual Property, Inc.

20080191797 - High pass filter circuit with low corner frequency: A high pass filter circuit having a signal input terminal and a signal output terminal. The high pass filter circuit is provided with a voltage source, first and second inverters, and a capacitor. The voltage source provides a DC bias voltage. The first inverter couples to the voltage source to... Agent: Madson & Austin

20080191798 - Bootstrap voltage generating circuits: A bootstrap voltage generating circuit includes a bias circuit having a first end coupled to a first power source node having an operation voltage, and a second end coupled to a low voltage reference potential, wherein a voltage at the first end is related to the operation voltage in a... Agent: Slater & Matsil, L.l.p.

20080186060 - Circuit for matching semiconductor device behavior: A selection circuit. The selection circuit comprises a logic circuit, an array of sub-circuits and a switching circuit electrically coupled to each other. The selection circuit is subjected to a first operating condition. The switching circuit selects a group of sub-circuits from the array. The selection circuit generates a first... Agent: Schmeiser, Olsen & Watts

20080186061 - Common-mode insensitive sampler: An approach to rejecting input common-mode voltage variations in a sampler/converter that avoids the use of a differential amplifier in the signal path, and without introducing added distortion or noise. In one embodiment, the input common-mode variations are sensed on a pair of matched resistors that straddle the common mode... Agent: Hamilton, Brook, Smith & Reynolds, P.C.

20080186064 - Digital programmable frequency divider: A digital programmable frequency divider is constructed of Rapid Single Flux Quantum (RSFQ) logic elements. The logic elements may include an RSFQ non-destructive readout cell (NDRO), and RSFQ D flip-flop and an RSFQ T flip-flop. A digital word comprising N bits is used to control the amount of frequency division... Agent: Allen, Dyer, Doppelt, Milbrath & Gilchrist P.A.

20080186062 - Frequency divider: A frequency divider providing an odd integer division factor comprising a binary counter (10) providing an even integer division factor, which is the first even number smaller than the odd division factor, the binary counter having a clock input for receiving a periodical clock signal (Ck) having a frequency. The... Agent: Nxp, B.v. Nxp Intellectual Property Department

20080186063 - Reduced-noise frequency divider system: Embodiments of a reduced noise reduction system (“RNFDS”) include a frequency divider and a resampler in signal communication with the frequency divider. The frequency divider receives an input signal and, in response, produces a divided signal. The input signal has a first frequency and the divided signal has a second... Agent: Agilent Technologies Inc.

20080186065 - Method and apparatus for pulse generation: A method and apparatus for generating a desired pulse waveform including: dividing the desired pulse waveform into a plurality of line segments; assigning to each line segment at least a segment identification, a segment initial value, and a segment duration to form a waveform description; providing the waveform description to... Agent: Pearne & Gordon LLP

20080186066 - Phase locked loop and phase locking method: A phase locked loop includes a charge pump, a voltage-current converter, and a current controlled oscillator. The charge pump generates a pump current based on a bias voltage and a phase difference detection signal, in which the pump current is for adjusting a control voltage. The voltage-current converter is self-biased,... Agent: Mills & Onello LLP

20080186067 - Delayed locked loop circuit: A Delayed Locked Loop Circuit of DLL comprises a buffer that receives a power-down signal and an inverted signal of a first clock signal; first and second delay lines an output device that outputs signals corresponding to the output signals of the first and second delay lines respectively; a replica... Agent: Ladas & Parry LLP

20080186068 - Circuit and technique for adjusting and accurately controlling clock duty cycles in integrated circuit devices: A circuit and technique for adjusting and accurately controlling clock duty cycles in integrated circuit devices in which only N-channel current regulating transistors are used in the voltage-controlled inverters and both the rising and falling edges can be adjusted by cascading two such inverters. The potential for cascading of these... Agent: Hogan & Hartson LLP

20080186069 - Design structure for dynamic latch state saving device and protocol: The invention comprises a design structure for a dynamic voltage state-saving latch electrical circuit comprising a charge device adapted as a storage element, an integrated recovery mechanism, a supply voltage rail connected to the charge device, a hold signal allocated to the integrated recovery mechanism, a data signal input allocated... Agent: Frederick W. Gibb, Iii Gibb & Rahman, LLC

20080186070 - Higher operating frequency latch circuit: A latch or flip flop circuit with an increased operating frequency is disclosed. In particular, the operating frequency of the latch is increased by reducing the set up time of the latch circuit. A regenerative circuit is provided between the transmission gate of the latch circuit and the data output.... Agent: Texas Instruments Incorporated

20080186071 - On-chip electrically alterable resistor: A programmable, electrically alterable (EA) resistor, an integrated circuit (IC) chip including the EA resistor and integrated analog circuits using on-chip EA resistors. Phase change storage media form resistors (EA resistors) on an IC that may be formed in an array of parallel EA resistors to set variable circuit bias... Agent: Law Office Of Charles W. Peterson, Jr. Yorktown

20080186072 - Controllable delay line and regulation compensation circuit thereof: A controllable delay line includes an anti-jitter unit, a dependent current source, a first current mirror, a second current mirror, a regulation capacitor, a compensation capacitor and an output buffer unit. The anti-jitter unit receives a first bias voltage and produces a second bias voltage based on the first bias... Agent: J C Patents, Inc.

20080186073 - Determining a time base for a microcontroller: The invention relates to a method for producing a time base for a microcontroller and a simple circuit arrangement therefor, which comprises an RC-element having a specific time constant, said element being connected to a connection of the microcontroller. According to said method, the capacitor of the RC element is... Agent: Fish & Richardson PC

20080186074 - Circuit and method for reducing pin count of chip: A configured setting circuit and method thereof is disclosed. The configured setting circuit includes a multi-phase clock generator, a plurality of terminals, and a decision circuit. The multi-phase clock generator generates a plurality of multi-phase signals with different phases to be outputted via the terminals. The decision circuit detects a... Agent: North America Intellectual Property Corporation

20080186075 - Level shifter of semiconductor device and method for controlling duty ratio in the device: A level shifter of a semiconductor device and method of controlling a duty ratio are provided. The level shifter includes first and second PMOS transistors having sources to which a power supply voltage is applied, first and second NMOS transistors having sources to which a ground voltage is applied, third... Agent: Mills & Onello LLP

20080186076 - Level detector, communication apparatus, and tuner: A level detector includes a comparing circuit and an integrating circuit. The comparing circuit generates pulses each having its width corresponding to the length of a time period during which the strength of an input signal is higher than a reference value. Alternatively, the comparing circuit may generate pulses each... Agent: Birch Stewart Kolasch & Birch

20080186077 - Low-voltage comparator-based switched-capacitor networks: Described is a switched-capacitor network and method for performing an analog circuit function. The circuit includes a switched-capacitor network, a comparator, and a voltage-offset network. The switched-capacitor network includes multiple switches, each having a respective threshold voltage and connected to one of a high-limit voltage, a low-limit voltage, and electrical... Agent: Guerin & Rodriguez, LLP

20080186078 - Method for selecting an input media source: System and method for changing a current input terminal of a user device. In one embodiment of the invention, a method includes receiving an input terminal change request, requesting that a current input terminal be changed from a first input terminal to a second input terminal. The method may further... Agent: Crowell & Moring LLP Intellectual Property Group

20080186079 - Semiconductor switch: A challenge in outputting a voltage near the midpoint potential in a semiconductor switch which operates based on a low voltage power supply is to avoid a decrease in operation speed and a deterioration in accuracy of the output voltage which would be caused due to an increase in ON-resistance... Agent: Mcdermott Will & Emery LLP

20080186081 - Charge pump circuit: Each of a plurality of pump stages has an input node and an output node and performs a charge pump operation in response to any one of the first and second clock signals. The plurality of pump stages include a first pump stage, in which a charge transfer transistor is... Agent: Mcdermott Will & Emery LLP

20080186080 - Device for supplying temperature dependent negative voltage: A negative voltage supply device includes a negative voltage detector and a negative voltage pumping unit. The negative voltage pumping unit pumps a negative voltage in response to a detection signal. The negative voltage detector detects a level of a negative voltage by using a first element and a second... Agent: Mcdermott Will & Emery LLP

20080186082 - Digital adaptive voltage supply: Measurement circuit components are included in an integrated circuit fabricated on a semiconductor substrate. These measurement circuits include registers that are connected to a voltage regulation circuit that provides the integrated circuit voltage source and to a power management circuit. These measurement circuits provide signals to control the voltage regulation... Agent: Ibm Corporation

20080186083 - Apparatus and method for controlling voltage and frequency using multiple reference circuits: The apparatus includes at least one reference circuit representative of a behavior of at least one estimated circuit, whereas the at least one estimated circuit includes transistors of multiple types; and monitoring circuitry adapted to monitor a behavior of at least one reference circuit and to determine a characteristic of... Agent: Freescale Semiconductor, Inc. Law Department

20080186085 - On-chip electrically alterable resistor: A programmable, electrically alterable (EA) resistor, an integrated circuit (IC) chip including the EA resistor and integrated analog circuits using on-chip EA resistors. Phase change storage media form resistors (EA resistors) on an IC that may be formed in an array of parallel EA resistors to set variable circuit bias... Agent: Law Office Of Charles W. Peterson, Jr. Yorktown

20080186084 - Voltage stabilizing circuit for chips and method thereof: A voltage stabilizing circuit for chips and the method thereof are disclosed. The circuit and the method thereof are applied to chips with at least one non-wire bonded I/O circuit. The driver circuit of the I/O circuit includes a plurality of transistors. The method of voltage stabilizing involves causing at... Agent: Rosenberg, Klein & Lee

20080186086 - Logical battery partitions: A logical battery partitioning approach is disclosed. In one embodiment, a power management system in a portable computing device having a plurality of subsystems can include: (i) a battery coupled to a plurality of subsystems; (ii) a first battery variable provided to a first subsystem to indicate a characteristic of... Agent: Trellis Intellectual Property Law Group, PC

20080186087 - Method and apparatus for reducing electromagnetic interference: An apparatus for reducing electromagnetic interference is provided. The apparatus includes a receiving module, a first comparing module, and a frequency spreading module. The receiving module receives a first signal with a first frequency and a second signal with a second frequency. The first comparing module is used for comparing... Agent: Birch Stewart Kolasch & Birch