Miscellaneous active electrical nonlinear devices, circuits, and systems inventions 07/08

20080180134 - Electronic circuit for measurement of transistor variability and the like: An electronic circuit includes an output terminal and at least a first measuring FET. The second drain-source terminals of a plurality of FETS to be tested are interconnected with the first drain-source terminal of the first measuring FET and the output terminal. The second drain-source terminal of the first measuring... Agent: Ryan, Mason, & Lewis, LLP

20080180135 - Hysteresis circuit applied to comparator and amplifier circuit thereof: A hysteresis circuit applied to a comparator and an amplifier circuit thereof are provided. A hysteresis circuit is disposed on a positive feedback path of the comparator, such that the comparator resists noise interferences, and the hysteresis circuit has a feature of not affecting the feedback voltage signal, thereby making... Agent: Rabin & Berdo, PC

20080180136 - Pre-charge sample-and-hold circuit: A precharge sample-and-hold circuit is formed by coupling a buffer with an input port and making use of a switch to conduct the circuit between the buffer and a total load capacitor for precharging according the state of a sample-and-hold circuit. When the sample-and-hold circuit is in the sample mode,... Agent: Rosenberg, Klein & Lee

20080180137 - Ignition coil: An ignition coil includes a coil portion and an igniter. The coil portion has a primary coil, a secondary coil, and a coil case. The primary coil and the secondary coil are disposed in the coil case. The igniter is disposed on one end side of the coil portion. The... Agent: Nixon & Vanderhye, PC

20080180139 - Cmos differential rail-to-rail latch circuits: A CMOS rail-to-rail differential latch is provided in which a plurality of cross-coupled devices pull first and second nodes of the latch to opposite rail-to-rail voltages. Desirably, first and second output isolating elements have inputs coupled to the first and second nodes, the output isolating elements being operable to output... Agent: International Business Machines Corporation Dept. 18g

20080180138 - Method of determining fractional divide ratio using sigma-delta modulator: The invention relates to method of determining a fractional division ratio using a sigma-delta modulator. In this method, the fractional division ratio of the sigma-delta modulator is set as k/q, where k is an integer input value of the sigma-delta modulator, and q is a value preset to determine a... Agent: Lowe Hauptman Ham & Berner, LLP

20080180140 - Method and system for synchronizing phase of triangular signal: A multiplicity of electronic devices is provided to generate triangular wave signals variable between an upper and lower limit voltages by charging or discharging capacitors. One of the triangular wave signals serves as a master triangular wave signal for controlling the phases of the remaining (or slave) triangular wave signals.... Agent: Hogan & Hartson L.L.P.

20080180141 - Method and apparatus for producing triangular waveform with low audio band noise content: A triangular waveform generator includes a square waveform clock circuit and an active integrator. The active integrator receives input from the square waveform clock circuit and generates a triangular waveform output. An active feedback network is operatively added to the active integrator to reduce the audio band noise content in... Agent: The Hecker Law Group, PLC Suite 2300

20080180142 - Phase locked loop with phase rotation for spreading spectrum: A phase locked loop (PLL) with phase rotation spreading includes a phase detector, a charge pump, a filter, a voltage controlled oscillator (VCO) and a selector. The phase detector receives a reference clock signal and a feedback clock signal to thereby produce an error signal. The charge pump converts the... Agent: Bacon & Thomas, PLLC

20080180143 - Phase locked circuit: A phase locked circuit includes a locked loop circuit having a phase comparator, a voltage controlled oscillator, and a variable frequency divider which divides a clock signal fvco output from the voltage controlled oscillator by n and outputs it. Additionally, the phase locked circuit includes a band pass filter part... Agent: Harness, Dickey & Pierce, P.L.C

20080180144 - Phase detector circuit and method therefor: The disclosure relates to phase detectors. Charge up and charge down signals that are generated by a phase detector cause i) following detection of a first edge of a reference clock signal, switching on of a switching transistor of sink current; ii) following detection of an edge of a feedback... Agent: Borden Ladner Gervais LLP Anne Kinsman

20080180146 - Adjustment mechanism for source synchronous strobe lockout: An apparatus for adjusting a lockout time in a source synchronous strobe receiver, including a delay-locked loop (DLL) and receivers. The DLL receives a reference clock and generates adjusted and encoded vectors, both indicating a first time period. A select vector is employed to select a delayed version of the... Agent: Huffman Law Group, P.C.

20080180145 - Apparatus and method for locking out a source synchronous strobe receiver: An apparatus for locking out a source synchronous strobe receiver, including a delay-locked loop (DLL) and one or more receivers. The DLL receives a reference clock, and generates a select vector and an encoded select vector that both indicate a lockout time. The select vector is employed to select a... Agent: Huffman Law Group, P.C.

20080180149 - Delay locked loop circuit having coarse lock time adaptive to frequency band and semiconductor memory device having the delay locked loop circuit: Provided are a DLL circuit having a coarse lock time adaptive to a frequency band of an external clock signal and a semiconductor memory device having the DLL circuit. The DLL circuit includes a delay circuit, a replica circuit, and a phase detector. The phase detector generates a first comparison... Agent: Mills & Onello LLP

20080180147 - Encoded mechanism for source synchronous strobe lockout: An apparatus for locking out a source synchronous strobe receiver, including a delay-locked loop (DLL) and receivers. The DLL receives a reference clock, and generates a select vector and an encoded select vector. The select vector is employed to select a delayed version of the reference clock that lags the... Agent: Huffman Law Group, P.C.

20080180148 - Receiver mechanism for source synchronous strobe lockout: An apparatus for locking out a source synchronous strobe receiver, including a delay-locked loop (DLL) and one or more receivers. The DLL receives a reference clock, and generates a select vector and an encoded select vector that both indicate a lockout time. The select vector is employed to select a... Agent: Huffman Law Group, P.C.

20080180150 - Digital circuit semiconductor device, and clock adjusting method: A digital circuit 10a is provided with clock operation circuits which output data signals in accordance with input timing of a clock signal, and the digital circuit 10a comprises: variable delay circuits 13-1 and 13-2 which give predetermined delay times to the clock signal or the data signals; a delay... Agent: Muramatsu & Associates

20080180151 - Flexible oscillator structure: An oscillator structure has a sync signal processor with an input interface for an external clock based sync signal and an output interface for a duty cycle indication signal depending on a signal property of the sync signal and an oscillator with an input interface for the duty cycle indication... Agent: Eschweiler & Associates LLC

20080180152 - Method of phase noise reduction in a soi type master-slave circuit: The invention provides a design method for reducing phase noise of an electronic circuit comprising a master section and a slave section, said sections including SOI type transistors, characterised in that, first, the floating body transistors which are involved in the degradation of said phase noise are located, then their... Agent: Blakely Sokoloff Taylor & Zafman LLP

20080180153 - Soft error robust flip-flops: A flip-flop circuit is provided with an improved robustness to radiation induced soft errors. The flip-flop cell comprises the following elements. A transfer unit for receiving at least one data signal and at least one clock signal, a storage unit coupled to the transfer unit and a buffer unit coupled... Agent: Gowling Lafleur Henderson LLP

20080180154 - Digital delay circuit: A digital time delay circuit is provided in which fabrication process variations and temperature effects on the switching threshold level of digital circuits utilized in the timing delay circuits are substantially eliminated.... Agent: Donald J Lenkszus

20080180155 - Data output clock generating circuit and method of generating data output clock of semiconductor memory apparatus: A data output clock generating circuit for a semiconductor memory apparatus includes a rising data output clock generating unit configured to combine a rising clock with a rising clock extraction signal generated in response to a rising output enable signal and a falling clock, to generate a rising data output... Agent: Venable LLP

20080180156 - Mixer circuit: A mixer using a small signal differential model includes a load circuit, a switch quad, and a transconductor. The switch quad further including a first current path and a second current path is coupled to the load circuit. The connecting node of the switch quad and the load circuit is... Agent: Madson & Austin

20080180157 - Semiconductor integrated circuit device and power control method thereof: A semiconductor IC includes a logic block, and a voltage control circuit controlling an operating voltage supplied into the logic block. The voltage control circuit controls the operating voltage to be increased in a stepwise fashion during an initial operation of the logic block.... Agent: F. Chau & Associates, LLC

20080180158 - Driving circuit for an emitter-switching configuration of transistors: A driving circuit for an emitter-switching configuration of transistors having first and second control terminals connected to the driving circuit, forms a controlled emitter-switching device having in turn respective collector, source and gate terminals. The driving circuit comprises a driving block coupled between the collector terminal and the source terminal... Agent: Seed Intellectual Property Law Group PLLC

20080180159 - Clock gater with test features and low setup time: A clock gater circuit comprises a plurality of transistors having source-drain connections forming a stack between a first node and a supply node. A given logical state on the first node causes a corresponding logical state on an output clock of the clock gater circuit. In one embodiment, a first... Agent: Lawrence J. Merkel Meyertons, Hood, Kivlin, Kowert & Goetzel, P.C.

20080180160 - High voltage dual gate cmos switching device and method: A dual gate drain extension field effect transistor assembly comprises a first FET device having a source, a gate and a drain extension region. The first FET device's gate is electrically coupled to a constant voltage source. A second FET device has a source, a drain, and a gate, and... Agent: Schwegman, Lundberg & Woessner / Infineon

20080180161 - Bias current generating apparatus with adjustable temperature coefficient: There is provided a bias current generating apparatus capable of providing a bias current where a characteristic change is compensated, to one of an analog circuit and RF circuit where various characteristic changes occur according to a temperature, by generating bias currents having a plurality of temperature coefficients. The apparatus... Agent: Lowe Hauptman Ham & Berner, LLP

20080180163 - Boosting charge pump circuit: In order to resolve a problem of the conventional technique in which there is a charge pump capacitance which is not used when a boosting method of the charge pump is changed, in a charge pump circuit unit, a connection switching terminal selects a power source voltage, a logically-inverting buffer... Agent: Mcginn Intellectual Property Law Group, PLLC

20080180162 - Fast turn on and off speed in pll cascoded charge pump: A charge pump includes a first switch coupled between a first voltage source and a first node, second switch coupled between the first node and a second node, a third switch coupled between the second node and a third node, the third node is for outputting from the charge pump.... Agent: North America Intellectual Property Corporation

20080180164 - Active filter for reduction of common mode current: An active filter for reducing the common mode current in a pulse width modulated drive circuit driving a load, said drive circuit comprising an a-c source, a rectifier connected to said a-c source and producing a rectified output voltage connected to a positive d-c bus and a negative d-c bus,... Agent: Ostrolenk Faber Gerb & Soffen

20080180165 - System and method for reducing noise in sensors with capacitive pickup: An apparatus and method are provided for reducing noise in a capacitive sensor (200). One apparatus includes a gain stage (210) including an output, the gain stage configured to generate a first signal having a noise component and a second signal having a desired output component and the noise component,... Agent: Ingrassia Fisher & Lorenz, P.C. (fs)

20080174341 - Analog voltage latch: An analog voltage latch for use in a controller for controlling a motor equipped electric bicycle, includes a window comparator for comparing an analog voltage latch output and an analog input voltage to produce a comparison result, an S-R latch for producing HIGH or LOW according to the comparison result,... Agent: Greenblum & Bernstein, P.L.C

20080174342 - Comparator with complementary differential input stages: A comparator comprises complementary (e.g. NMOS and PMOS) comparator cells having overlapping common mode input voltage ranges which together extend approximately from rail to rail. A digital logic arrangement, including edge detectors, gates, and a latch, is responsive to transitions at the outputs of the comparator cells to set the... Agent: Smart & Biggar P.o. Box 2999, Station D

20080174343 - Data receiver and data receiving method: A data receiver and a data receiving method in which the data receiver generates two comparison signals based on amplitude modulated differential input signals, amplifies the comparison signals, compares amplified signals, and outputs logic operation results based on the amplitude modulated differential input signals and the comparison signals, thereby detecting... Agent: F. Chau & Associates, Llc

20080174344 - Bifurcate buffer: A buffer includes a plurality of serial inputs, a plurality of de-serializers, each coupled to a respective input, a plurality n of buffers and a media access controller having inputs coupled to the plurality of de-serializers, data outputs coupled to the buffers, and two control outputs coupled to respective buffers... Agent: Henneman & Associates, Plc

20080174345 - Method and apparatus for measuring the duty cycle of a digital signal: The disclosed methodology and apparatus measures the duty cycle of a clock signal. A variable duty cycle circuit receives a clock signal from a clock signal generator. The variable duty cycle circuit adjusts the duty cycle of the clock signal by an amount dependent on a duty cycle index value... Agent: Mark P. Kahler

20080174346 - Differential amplitude controlled sawtooth generator: A dual differential sawtooth signal generator includes a first sawtooth voltage generator that has a first capacitor and a second capacitor that are alternately charged with a feedback control source current from a low voltage reference voltage level. A second sawtooth voltage generator has a first discharge capacitor and a... Agent: Schwegman, Lundberg & Woessner / Atmel

20080174347 - Clock synchronization system and semiconductor integrated circuit: A clock synchronization system includes a phase-locked loop to generate a multiplied clock based on a reference clock, a frequency divider to generate a plurality of frequency-divided clocks based on the multiplied clock, and a frame pulse generator to generate a frame pulse by frequency-dividing the reference clock, wherein the... Agent: Sughrue Mion, Pllc

20080174348 - Sub-pixel generation for high speed color laser printers using a clamping technique for pll (phase locked loop) circuitry: Methods and apparatus for optimizing the phase lock loop circuitry of sub-pixel clock generators for situations where frequent switching between different system printing speeds, and hence clock frequencies are required. An optimizing circuit is associated with a sub-pixel clock generator for clamping an input voltage to a voltage controlled oscillator... Agent: Fay Sharpe / Xerox - Rochester

20080174349 - Wide-locking range phase locked loop circuit using adaptive post division technique: A wide-locking range phase locked loop circuit includes a decision unit and a closed loop connection comprising a phase frequency detector, a charge pump, a loop filter, a voltage controlled oscillator, and a multi-modulus divider. The decision unit receives a phase difference signal outputted from phase frequency detector and the... Agent: Wpat, Pc

20080174350 - Dll circuit and method of controlling the same: A DLL circuit includes a duty ratio detection unit that detects a duty ratio of a rising clock and a duty ratio of a falling clock, thereby outputting a duty ratio detection signal. A correction control unit generates a correction control signal in response to the duty ratio detection signal.... Agent: Venable LLP

20080174351 - Pulse width modulation circuit and switching amplifier using the same: A pulse width modulation circuit 1 of the present invention changes the voltage of a first integration circuit C1 during the first period T1 of the clock signal MCLK based on a current based on an audio signal eS, changes the voltage of the first integration circuit C1 based on... Agent: Mark D. Saralino (general) Renner, Otto, Boisselle & Sklar, LLP

20080174352 - Phase adjusting device and related art thereof: A characteristic detecting unit detects characteristics of a digital imaged signal at every phase shift interval set in advance. A timing adjustment unit gives a phase adjustment instruction of a pulse so as to converge to an imaging phase in the digital imaged signal at which the characteristics are a... Agent: Mcdermott Will & Emery LLP

20080174353 - Path delay adjustment circuitry using programmable driver: A method and system for using a programmable driver to dynamically adjust the path delay of a circuit. The path delay adjustment circuit in the illustrative embodiments comprises two or more latches, wherein each latch receives a signal, processes the signal, and generates an output. Compare logic connected to the... Agent: Ibm Corp (ya) C/o Yee & Associates Pc

20080174354 - Clock generating circuit and method thereof: A clock generating circuit and method therefor are provided, which includes a control unit, a first oscillating module, a second oscillating module, a status control unit, and a multiplexer. The control unit is used for outputting a first control signal and a second control signal so as to drive the... Agent: Wpat, Pc

20080174355 - Integrated circuit apparatus: a first current source and a second current source; a resistor connected between the first current source and a reference potential portion; a switched capacitor circuit having a variable capacitor, first switch and a second switch, the first switch and second switch alternately switching capable of charging a voltage to... Agent: Arent Fox LLP

20080174356 - Wave detector circuit: A wave detector circuit includes: a first transistor having its base and collector connected together, the first transistor receiving an AC signal and a reference voltage at its base and collector; a second transistor having its base connected to the base of the first transistor through a resistance, the second... Agent: Leydig Voit & Mayer, Ltd

20080174357 - Semiconductor device: A semiconductor device having a switch includes a first FET connected to a terminal and a second FET of a stage following that of the first FET. The gate width of the first FET is greater than that of the second FET. A sum of lengths of a source electrode... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080174358 - Control circuit of p-type power transistor: A control circuit for P-type power transistor. The P-type power transistor includes a gate coupled between an input voltage and an output voltage. A first switch is coupled between a first voltage and the gate. A current source provides a first current, and is coupled to a second voltage. A... Agent: Joe Mckinney Muncy

20080174359 - Semiconductor integrated circuit: A substrate bias technique is used in an active mode enabling a high yield, and an operating consumption power and the fluctuation of a signal delay in signal processing are reduced in the active mode. The additional PMOS and NMOS of the additional capacitance circuit are produced in the same... Agent: Miles & Stockbridge Pc

20080174361 - Apparatus and method for phase lock loop gain control using unit current sources: A gain compensator compensates for the gain variation of a varactor-tuned voltage tuned oscillator (VCO) in a phase lock loop (PLL). The VCO includes a parallel LC circuit having multiple fixed capacitors that can be switched-in or switched-out of the LC circuit according to a capacitor control signal to perform... Agent: Mcandrews Held & Malloy, Ltd

20080174360 - Charge pump circuit for high voltage generation: A circuit and method are given, to realize a high efficiency voltage multiplier for integrated circuits generating an internal and flexible positive or negative high voltage on-chip supply voltage from low external positive or negative supply voltages or ground. Applying multi-phase control signals to voltage boost internal nodes allows for... Agent: Jen-shou Hsu

20080174363 - Output stage for electronic devices integrated on a semiconductor substrate, in particular for high frequency applications and corresponding method: An output stage may include an input terminal receiving an input signal, an output terminal coupled to an external load, and a pre-buffer coupled to the input terminal and including an enable terminal receiving a general enable signal and a first output terminal for supplying a first control signal. The... Agent: Allen, Dyer, Doppelt, Milbrath & Gilchrist P.a.

20080174362 - Voltage supply circuit and circuit device: A voltage supply circuit and a circuit device can reduce the noise in the output of the circuit when the power to the circuit is turned on and off and can shorten the time required to start or stop the operation of the circuit. When the supply of power to... Agent: Texas Instruments Incorporated

20080174364 - Internal supply-voltage generator of semiconductor memory device: An internal supply-voltage generator of a semiconductor memory device, which can be used both in a high-voltage test mode and in a normal operation mode, maintains a constant response speed in the normal operation mode and includes; a comparator comparing a reference voltage with an internal supply voltage and outputting... Agent: F. Chau & Associates, Llc

20080169843 - Method and apparatus for implementing efuse sense amplifier testing without blowing the efuse: A method and apparatus implement effective testing of a sense amplifier for an eFuse without having to program or blow the eFuse, and a design structure on which the subject circuit resides is provided. After initial processing of the sense amplifier, testing determines whether the sense amplifier can generate a... Agent: Ibm Corporation RochesterIPLaw Dept 917

20080169844 - Voltage detection circuit in an integrated circuit and method of generating a trigger flag signal: An integrated circuit that includes at least one tunneling device voltage detection circuit for generating a trigger flag signal. The tunneling device voltage detection circuit includes first and second voltage dividers receiving a supply voltage and having corresponding respective first and second internal node output voltages. The first and second... Agent: Downs Rachlin Martin PLLC

20080169845 - Sensors using a passive s/h and dda: A CMOS image sensor includes a photosensitive region for collecting charge in response to incident light; a charge-to-voltage mechanism for receiving the charge from the photosensitive region and converting the charge to a voltage; an amplifier for receiving and amplifying the voltage; a sample and hold circuit includes (i) a... Agent: Pamela R. Crocker Eastman Kodak Company

20080169846 - High efficiency nltl comb generator using time domain waveform synthesis technique: A device and method are disclosed for synthesizing a waveform having pulse segments. An exemplary generator can include units having a time delay element and pulse generator generating the pulse segments. An input divider divides an input signal into signal instances that propagate through the units and an output combiner... Agent: Posz Law Group, PLC

20080169847 - Driver and driver/receiver system: A driver includes an output circuit which converts an input signal to a predetermined output waveform and outputs the predetermined waveform to first and second output terminals, a first output resistor having one end connected to the first output terminal, a second output resistor having one end connected to the... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.C.

20080169848 - High-speed leaf clock frequency-divider/splitter: A novel clock splitter that has a local internal clock frequency-divider is presented. The clock splitter comprises an oscillator clock splitter, wherein the oscillator clock splitter splits an oscillator clock signal into a B clock and a C clock; a clock frequency-divider, wherein the clock frequency-divider selectively suppresses clock pulses... Agent: Ibm Corporation

20080169849 - System and method for implementing a dual-mode pll to support a data transmission procedure: A system and method for effectively utilizing a dual-mode phase-locked loop to support a data transmission procedure includes a voltage controlled oscillator that generates a receiver clock signal in response to VCO input control signals. A binary phase detector generates a BPD output signal during a BPD mode by comparing... Agent: Gregory J. Koerner Redwood Patent Law

20080169850 - Phase-locked loop circuit: A phase-locked loop circuit comprises a phase frequency detector, a charge pump associated with a loop capacitance, and a voltage controlled oscillator. The phase frequency detector receives a reference clock signal on a first input and a feedback signal from the voltage controlled oscillator on a second input. The charge... Agent: Texas Instruments Incorporated

20080169853 - Apparatus for detecting and preventing a lock failure in a delay-locked loop: An apparatus for detecting a lock failure and correcting a duty cycle includes a lock failure detector configured to determine whether a first internal clock signal is locked to a second internal clock signal and to output a lock failure signal in response thereto, a duty cycle correction unit configured... Agent: Lee & Morse, P.C.

20080169851 - Delay locked loop: In a delay locked loop, a phase detector compares the phases of an input signal and an output signal; a delay line delays the input signal, wherein the delay line includes a plurality of unit delay elements connected in series and the value of the unit delay of each of... Agent: Jianq Chyun Intellectual Property Office

20080169852 - Delay locked loop circuits and method for controlling the same: A delay locked loop circuit and a method for controlling the same including a delay locked loop (DLL) circuit for receiving an external clock signal and generating an internal clock signal synchronized to the external clock signal includes at least two delay chains having different types of delay cells for... Agent: F. Chau & Associates, LLC

20080169854 - Method and device for determining trim solution: A trimming system for determining a trim solution for a semiconductor device includes an internal value generating circuit for generating an internal value based upon a counter value. The relationship between the internal delay value and an external reference is compared to determine if the counter value is a possible... Agent: Posz Law Group, PLC

20080169855 - Apparatus and method for correcting duty cycle of clock signal: An apparatus for correcting a duty cycle of an input clock signal to generate a digitally corrected clock signal includes a duty cycle detector, an analog duty cycle correcting unit, and a digital duty cycle correcting unit. The duty cycle detector generates a duty cycle signal indicating a respective duty... Agent: Law Office Of Monica H Choi

20080169856 - System and apparatus to activate electric triggers: The present invention provides a current impulse generator that is fed by a high voltage source. The high voltage from the source creates an electric field which turns into a corona current by means of a corona current source. The corona current source charges a floating electrode with electrostatic energy... Agent: John J. Martinez Md. Jd.

20080169857 - Hierarchical scalable high resolution digital programmable delay circuit: A hierarchical and modular clock programmable delay circuit structure is described that can achieve almost unlimited fine resolution and unlimited delay range. The same circuit may also be applied to critical circuits that require fine adjustment in timing applications. The modular design allows the circuit and its layout to be... Agent: International Business Machines Corporation

20080169858 - Source driver and level shifting apparatus thereof: The present invention discloses a source driver and a level shifting apparatus thereof. The level shifting apparatus is used for shifting a level of a data signal. The level shifting apparatus comprises a first charge pump and a level shifter. The first charge pump supplies a first pumped voltage based... Agent: Lowe Hauptman Ham & Berner, LLP

20080169859 - Drain-pumped sub-harmonic mixer for millimeter wave applications: A sub-harmonic mixer includes a first transistor having a source and a drain and a second transistor having a source connected to the source of the first transistor and a drain connected to the drain of the first transistor. A mixing transistor is configured to be biased in a linear... Agent: Keusey, Tutunjian & Bitetto, P.C.

20080169860 - Multichip package having a plurality of semiconductor chips sharing temperature information: A multichip package in which characteristics of all semiconductor chips mounted thereon can be controlled in response to a change in temperature. The multichip package can include a substrate and a plurality of semiconductor chips that are sequentially stacked and mounted on the substrate. In this case, a temperature detection... Agent: Baker & Mckenzie LLP Patent Department

20080169861 - Reference current source circuit and infrared signal processing circuit: The reference current source circuit 10 is provided with a current source circuit 1, a trimming fuse 3, a switching circuit 2 which connects/disconnects the current source circuit 1 and/from the trimming fuse 3, a NAND circuit 4 which controls the operation of the switching circuit 2, and a pull-down... Agent: Birch Stewart Kolasch & Birch

20080169862 - Semiconductor device and methods for controlling its patterns: A semiconductor device and a method for controlling its patterns is described where the electrical characteristics of the patterns formed by a double patterning process may be individually controlled responsive to critical dimensions (CDs) of the patterns. The method includes controlling two or more patterns having different CDs to optimally... Agent: Marger Johnson & Mccollom, P.C.

20080169864 - Booster circuit: A boosting circuit comprises a first boosting cell row and a second boosting cell row. The boosting circuit further comprises an analog comparison circuit for comparing the potential of boosting cells on the same stage, and selecting and outputting the lower or higher of the potentials. The potential of an... Agent: Mcdermott Will & Emery LLP

20080169863 - Semiconductor integrated circuit device including charge pump circuit capable of suppressing noise: In a semiconductor integrated circuit device including a charge pump circuit flowing an operating current therethrough, a current circuit is adapted to receive the operating current and a substantially constant current and generate an inverse relative to the operating current and the substantially constant current.... Agent: Sughrue Mion, PLLC

20080169865 - Internal voltage generating circuit: An internal voltage generating circuit includes a first detector that compares an internal voltage and a first reference voltage to output a first detection signal. A second detector compares a supply voltage and a second reference voltage to output a second detection signal. A loop selection oscillator performs an oscillation... Agent: Venable LLP

20080169866 - Combined charge storage circuit and bandgap reference circuit: A combined charge storage and bandgap reference is disclosed. In one embodiment, a system comprises a bandgap reference circuit; a charge storage circuit, wherein an output of the bandgap reference circuit is provided as an input to the charge storage circuit; and a control circuit in communication with the bandgap... Agent: Brinks Hofer Gilson & Lione

20080169867 - Design structure for low voltage applications in an integrated circuit: A design structure that includes at least one tunneling device voltage reference circuit for use in low voltage applications is disclosed. The tunneling device voltage reference circuit includes a pair of voltage dividing device stacks, one having a linear voltage output and the other having a non-linear voltage output. A... Agent: Greenblum & Bernstein, P.L.C

20080169868 - Layout structure of semiconductor device: In a layout structure capable of independent supply of a substrate or well potential from a power supply potential, further reduction in layout area is achieved. A reinforcing power supply cell is inserted in a cell line in which a plurality of cells are arranged in series. Each of the... Agent: Mcdermott Will & Emery LLP

20080169870 - Current drive circuit reducing vds dependency: A first transistor is provided in a first route and a second transistor is provided in a second route, the first route and the second route constituting a current mirror circuit. The sources of the transistors are grounded. In order to match VDS of the first transistor and that of... Agent: Cantor Colburn, LLP

20080169869 - Voltage reference circuit for low voltage applications in an integrated circuit: An integrated circuit that includes at least one tunneling device voltage reference circuit for use in low voltage applications is disclosed. The tunneling device voltage reference circuit includes a pair of voltage dividing device stacks, one having a linear voltage output and the other having a non-linear voltage output. A... Agent: Downs Rachlin Martin PLLC

20080169871 - Method and device for the filtering and analogue/digital conversion of analogue signal: The invention relates to a method for the filtering and analog/digital conversion of an incoming analog signal including an analog filtering of the incoming analog signal so as to filter the frequency components located outside a desired frequency band, and a conversion of the filtered analog signal to a digital... Agent: Allen, Dyer, Doppelt, Milbrath & Gilchrist P.A.

20080164913 - Peak-hold circuit and signal strength indicator using the peak-hold circuit: A peak-hold circuit includes a differential amplifier having first and second transistors as a differential pair, the first transistor receiving an input signal at its gate, a third transistor connected between a first power supply and an output node connecting a gate of the second transistor, connectivity of the third... Agent: Junichi Mimura Oki America Inc.

20080164914 - High accuracy zero crossing detector and method therefor: In one embodiment, a zero crossing detector couples a plurality of comparators in parallel and operates at least a portion of the comparators at different time periods.... Agent: Semiconductor Components Industries, LLC Intellectual Property Dept. - A700

20080164915 - Apparatus and method for automatically offsetting linear deviation of v/f converter: An apparatus and method for automatically offsetting the linear deviation of a V/F converter, the offset adjust pin of which is connected to a fixed resistance, and the frequency output pin of which is connected to a microcontroller unit (MCU) via an opto-isolator, a standard V/F transfer function being pre-stored... Agent: Hdsl

20080164916 - Broadband low noise complex regenerative frequency dividers: A regenerative frequency divider device including a plurality of multipliers, each of which has a first input port, a second input port and an output port; a first combiner coupled to the plurality of multipliers so as to receive an output signal from at least two of the multipliers; and... Agent: Motorola, Inc. Law Department

20080164917 - Circuits and methods for implementing sub-integer-n frequency dividers using phase rotators: Circuits and methods are provided for implementing programmable sub-integer N frequency dividers for use in, e.g., frequency synthesizer applications, providing glitch free outputs signals with minimal fractional spurs. Phase-rotating sub-integer N frequency dividers are programmable to provide multi-modulus division with a wide range of arbitrary sub-integer division ratios.... Agent: Frank V. Derosa, Esq. F. Chau & Associates, LLC

20080164918 - Pll loop bandwidth calibration: Systems and methodologies are described that facilitate calibration of the loop bandwidth of a phase-locked loop (PLL). Calibration for the loop bandwidth of a PLL as described herein can be performed by optimizing the loop response of the PLL. Optimization of the loop response of the PLL can be achieved... Agent: Amin, Turocy & Calvin LLP

20080164921 - Delay locked loop for high speed semiconductor memory device: A delayed locked loop supports increased operation frequency in a semiconductor memory device. An output driver for use in a delay locked loop includes a first driving block for receiving an output from the delay locked loop to generate a first DLL clock for outputting read data corresponding to a... Agent: Mcdermott Will & Emery LLP

20080164920 - Dll circuit and method of controlling the same: A DLL circuit includes a duty ratio correction unit that corrects the duty ratios of first and second delay clocks duty ratio to generate first and second correction clocks. A duty ratio detection unit detects the duty ratios of the first and second correction clocks, thereby generating first and second... Agent: Venable LLP

20080164919 - Semiconductor memory device and method for driving the same: A semiconductor memory device includes: a delay locked loop (DLL) for delaying an external clock to generate a DLL clock; an output control unit for generating a select signal based on a column address strobe (CAS) latency signal and a delay time corresponding to a total delay time of the... Agent: Mcdermott Will & Emery LLP

20080164922 - Data output strobe signal generating circuit and semiconductor memory apparatus having the same: A data output strobe signal generating circuit includes a duty cycle correcting unit that corrects the duty ratio of an input clock in response to a control signal to generate a corrected clock. A data output strobe signal generating unit receives the corrected clock and generates a data output strobe... Agent: Venable LLP

20080164923 - Delay circuit and electronic device including delay circuit: A delay circuit includes: a current control circuit which has n (n is 1 or larger natural number) control pins and a first output line, and is capable of controlling current outputted from the first output line in response to n control signals inputted to the corresponding n control pins;... Agent: Harness, Dickey & Pierce, P.L.C

20080164924 - Time based driver output transition (slew) rate compensation: Apparatus and method for controlling the driver output slew rate. The apparatus includes a driver circuit having an input signal and an output signal, where the driver circuit is structured and arranged to facilitate control of the slew rate of the output signal. A delay circuit having a time delay... Agent: Andrew M. Calderon Greenblum & Bernstein, P.L.C

20080164925 - Dual mode clock generator: There is a provided a dual mode clock generator that is applicable to a direct current-direct current converter of a power supply. The dual mode clock generator includes a frequency controller for controlling generation of charge and discharge; a current source unit for generating a charge, and generating a charge;... Agent: Lowe Hauptman Ham & Berner, LLP

20080164926 - Duty cycle correction circuit employing sample and hold charge pumping method: A duty cycle correction circuit employing a sample and hold charge pumping method is disclosed. The duty cycle correction circuit includes a duty regulator which generates an output signal by regulating duty of an input signal in response to a regulation voltage, and a charge pump which generates the regulation... Agent: Volentine & Whitt PLLC

20080164927 - Low-phase noise low-power accurate i/q generator using a dynamic frequency divider: A signal generator and method for generating a plurality of signals of differing phase. The signal generator comprises a first single-phase frequency divider locked with a 90° phase shift that includes a first output port providing a first output signal and a first internal node providing a first internal signal,... Agent: Downs Rachlin Martin PLLC

20080164928 - Phase interpolation apparatus, systems, and methods: A phase interpolator circuit may comprise a multiplexer circuit (MUX) coupled to a plurality of clock signals at MUX inputs and may provide a first clock signal and a second clock signal at MUX outputs that are out of phase with each other, a digital to analog converter circuit (DAC)... Agent: Schwegman, Lundberg & Woessner, P.A.

20080164929 - Electronic circuit wherein an asynchronous delay is realized: The electronic circuit contains a basic delay circuit (14). A delay is realized by activating the same basic delay circuit (14) a plurality of times in response to a single start signal before generating a response to that start signal. A control circuit (12) receives a start signal and an... Agent: Philips Intellectual Property & Standards

20080164930 - Phase interpolation apparatus, systems, and methods: A phase interpolator circuit may comprise a multiplexer circuit (MUX) to receive a plurality of clock signals at MUX inputs and to output a first clock signal and a second clock signal that are out of phase with each other, a digital to analog converter circuit (DAC) to convert a... Agent: Schwegman, Lundberg & Woessner, P.A.

20080164931 - Level shifter circuit: A level shifter circuit that properly operates even when the power supply voltage is unstable. A level shifter circuit includes a first level shifter unit, a second level shifter unit, and a latch unit. In the first level shifter unit, a transistor is connected to a power supply line to... Agent: Freescale Semiconductor, Inc. Law Department

20080164932 - Semi-buffered auto-direction-sensing voltage translator: In a method and system for translating voltage levels to interface electronic devices, a voltage translator is operable to perform the translation of voltage levels of the bidirectional signals exchanged between the electronic devices in accordance with an open-drain mode of operation and in accordance with a push-pull mode of... Agent: Texas Instruments Incorporated

20080164933 - Method and apparatus for multiple array low-power operation modes: In an embodiment of the invention, power consumption savings are realized in an array design. Such an array design, for example and not limitation, can be used in integrated circuits, including microprocessors as memory arrays, and or instruction cache arrays. Power consumption savings are realized in the array design by... Agent: Cantor Colburn LLP-ibm Yorktown

20080164934 - Connectors designed for ease of use: Headset connector systems and headset engaging connector systems are provided. Headset connector systems can include two or more headset connector contact regions. Headset engaging connector systems can include two or more headset engaging contact regions to provide at least one of power and data. The headset connector system or the... Agent: Ropes & Gray LLP

20080164935 - Signal splitting apparatus, video apparatus using the same, and signal splitting method: A signal splitting apparatus which improves the noise figure (NF) characteristic when an input signal is split and transmitting the input signal to another device even when the set does not operate, a video apparatus including the signal splitting apparatus, and a signal splitting method thereof The signal splitting apparatus... Agent: Sughrue Mion, PLLC

20080164936 - Apparatus and methods for adjusting performance of programmable logic devices: A programmable logic device (PLD) includes mechanisms for adjusting or setting the body bias of one or more transistors. The PLD includes a body-bias generator. The body-bias generator is configured to set a body bias of one or more transistors within the programmable logic device. More specifically, the body-bias generator... Agent: Law Offices Of Maximilian R. Peterson

20080164937 - Band gap reference circuit which performs trimming using additional resistor: A band gap reference circuit incorporating resistive trimming is disclosed. The band gap reference circuit includes an additional trimming resistor and a trimming unit which performs trimming by changing a resistance value of the trimming resistor.... Agent: Volentine & Whitt PLLC

20080164938 - Method and circuit for curvature correction in bandgap references with asymmetric curvature: A non-linear correction current ICTAT2 (current complementary to the square of absolute temperature) is generated from a current IPTAT (current proportional to absolute temperature) and a current ICTAT (current complementary to absolute temperature), both modified in a circuit having a topology and components which capitalize on the logarithmic relationship between... Agent: Texas Instruments Incorporated

20080164939 - Method for tuning a tunable filter: A method for tuning a tunable filter includes inputting a control signal to the tunable filter and tuning the configuration of the tunable filter according to the control signal. When the control signal is at any one of a plurality of predetermined states, a step size of a characteristic frequency... Agent: North America Intellectual Property Corporation

20080157819 - Increased reliability of data captures for signal predistortion: Determining a predistortion function includes sampling a signal to obtain a plurality of capture sets within a single sampling window. Each of the capture sets is analyzed to determine whether it satisfies preselected criteria. Example criteria include desired characteristics of a capture set average power, capture set peak power and... Agent: Carlson, Gaskey & Olds, P.c./alcatel-lucent

20080157820 - Apparatus to compare an input voltage with a threshold voltage: Apparatus to compare an input signal to a threshold level are disclosed. An example circuit described herein includes a Widlar bandgap circuit to receive the input signal, an intermediate stage coupled with the output of the Widlar bandgap circuit, and a final stage coupled with the output of the intermediate... Agent: Texas Instruments Incorporated

20080157821 - Programming circuit with feedback circuit: An exemplary programming circuit (40) includes an input terminal (42) configured for receiving an external high voltage signal, a driving circuit (20), a switch circuit (43) connected between the input terminal and the driving circuit, and a feedback circuit (45). When the external high voltage signal is larger than a... Agent: Wei Te Chung Foxconn International, Inc.

20080157822 - Zero-crossing point detection circuit: A zero-crossing point detection circuit includes a hot line input, a neutral line input, a first zero-crossing point output, and a first optical coupler. The first optical coupler includes a first light-emitting diode (LED) and a first optical transistor. The hot line input and neutral line input are respectively connected... Agent: Pce Industry, Inc. Att. Cheng-ju Chiang

20080157823 - Phase locked loop frequency synthesizer: A dynamic carrying method to prevent saturation of a sigma-delta modulator of a phase locked loop frequency synthesizer. The phase locked loop frequency synthesizer using the dynamic carrying method comprises a forward portion receiving a reference frequency signal and a first frequency signal to generate an output carrier signal; a... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20080157829 - Amplitude compensation circuit with programmable buffers: According to one exemplary embodiment, an amplitude compensation circuit includes a first composite programmable buffer for receiving a first input signal with a first input amplitude. The amplitude compensation circuit further includes a second composite programmable buffer for receiving a second input signal with a second input amplitude. The amplitude... Agent: Farjami & Farjami LLP

20080157824 - Analog voltage generator with self-biased capacitive feedback stage: Analog voltage drain with reduced current drain is achieved by a a new capacitive-divided feedback architecture. During the operational phase an op amp monitors a capacitively-divided fraction of the output voltage, and drives a current sink or source accordingly; during an initial phase the output is forced to the correct... Agent: Sandisk Corporation

20080157828 - Drive circuit, display apparatus using drive circuit, and evaluation method of drive circuit: For making outputs of a drive circuits accurate, the drive circuit is composed of a plurality of current signal generation circuits for outputting a current signal to each of a plurality of output units, a current signal output line to which outputs of the plurality of current signal generation circuits... Agent: Fitzpatrick Cella Harper & Scinto

20080157825 - Driving apparatus and driving method thereof: A driving apparatus and a driving method thereof are provided. The driving apparatus includes a digital to analog converter and a signal amplifier. The digital to analog converter is used for receiving a digital data and converting the digital data to an analog signal. The signal amplifier is coupled to... Agent: Jianq Chyun Intellectual Property Office

20080157827 - Input buffer circuit: An input buffer circuit is disclosed. The input buffer circuit includes a buffer configured to receive an input signal and differentially amplify and buffer the received input signal, and a current regulator for regulating the amount of current in the buffer at a turn-on level which depends on a level... Agent: Cooper & Dunham, LLP

20080157826 - Voltage driving circuit: A voltage driving circuit, suitable for being used in a pixel driving circuit, includes a storage unit for receiving a single-end data input signal and outputting a first voltage signal and a second voltage signal according to a content of the data input signal. The first voltage signal and the... Agent: Jianq Chyun Intellectual Property Office

20080157830 - Triangle oscillator and pulse width modulator: The present invention relates to an oscillator outputting two triangle waves having the same amplitude and whose phases are inverted; and a pulse width modulator using the oscillator. A capacitor 3 is charged or discharged by a charge pump circuit 2 controlled by a Schmitt circuit 1, and a voltage... Agent: Steptoe & Johnson LLP

20080157831 - Clock generation with reduced electromagnetic interference for dc-dc converters: A clock generator includes a current source for generating a constant current; a current mirror coupled between a supply voltage and the current source for generating a mirror current equal to the constant current multiplied by a predetermined value; and a charge control module coupled with the current source and... Agent: Howard Chen, Esq. Preston Gates & Ellis LLP

20080157832 - Power-on-reset circuit: A power-on-reset circuit for generating a reset voltage including a voltage divider and a temperature compensator that is insensitive to a change in PVT (Process, Voltage, Temperature) is disclosed. The temperature compensator compensates for a voltage variation of the voltage divider in an inversely proportional direction of a voltage variation... Agent: Sughrue Mion, Pllc

20080157833 - Method and apparatus for generating multi-phase signals: A method and apparatus for generating multi-phase clock signals. The multi-phase generating method includes: generating L reference clock signal groups having predetermined phase delay intervals from an external clock signal, wherein each reference clock signal group includes M sub reference clock signals; averaging phases of sub reference clock signals for... Agent: F. Chau & Associates, Llc

20080157834 - Charge pump for reducing current mismatch: A charge pump circuit is disclosed, including: a dummy current path comprising a first junction node; a normal current path comprising a second junction node; a switch, coupled between the dummy current path and the normal current path; wherein when the switch is closed a first voltage is at the... Agent: North America Intellectual Property Corporation

20080157835 - Oscillating apparatus: An oscillating apparatus is provided that includes: a filter circuit that includes a capacitor and outputs a control signal based on an amount of charge accumulated in the capacitor; an oscillator that outputs an oscillation signal of a frequency that is based on the control signal; a phase comparator that... Agent: Jianq Chyun Intellectual Property Office

20080157836 - Delay fixing loop circuit for reducing skew between external and internal clocks or between external clock and data, and a clock locking method thereof: The present invention relates to a delay fixing loop circuit including a delay fixing loop for reducing a skew between an external clock and a data, or between an external clock and an internal clock, and a clock locking method thereof. The delay fixing loop circuit includes a delay circuit... Agent: Ladas & Parry LLP

20080157837 - Delay locked loop (dll) circuit: A delay locked loop (DLL) circuit is disclosed. The DLL circuit includes a first delay locked loop (DLL) configured to receive a plurality of first clock signals, delay each of the first clock signals by a predetermined period of time in response to a first control signal, and generate a... Agent: Cooper & Dunham, LLP

20080157838 - Delay locked loop and method for operating thereof: A delay locked loop is disclosed which includes a clock selector for selecting and outputting any one of normal-phase and reverse-phase external clocks in response to a clock selection information signal, a first delay line for delaying an output signal from the clock selector by a predetermined amount of time,... Agent: Cooper & Dunham, LLP

20080157840 - Systems and methods for adding a delay to a signal: Systems and methods for transmitting a signal having a desired phase at the device are disclosed. The systems and methods further include determining a signal path length to a device over a transmission line and adding a delay to a signal to be transmitted over the transmission line. The determination... Agent: Texas Instruments Incorporated

20080157839 - Time-to-digital converter with non-inverting buffers, transmission gates and non-linearity corrector, soc including such converter and method of phase detection for use in synthesizing a clock signal: A time-to-digital converter (TDC), a system-on-chip including a TDC, a method of phase detection for use in synthesizing a clock signal and a non-linearity corrector for a TDC. In one embodiment, the TDC includes a chain of delay elements configured to receive a clock signal and generate delayed clock signals.... Agent: Texas Instruments Incorporated

20080157841 - Self-correcting buffer: In general, in one aspect, the disclosure describes an apparatus having a capacitor to receive an input signal and to block DC portion of the incoming signal. A buffer is used to receive the DC blocked incoming signal and output an outgoing signal. A low pass filter is used to... Agent: Ryder Ip Law C/o Intellevate, Llc

20080157842 - Mtcmos flip-flop circuit: Disclosed is a multi-threshold CMOS (MTCMOS) flip-flop circuit. The MTCMOS flip-flop circuit includes a data input unit including an inverter for receiving an input data signal, inverting the input data signal and then outputting an inverted data signal; a clock signal generator including an inverter for receiving an input clock... Agent: Saliwanchik Lloyd & Saliwanchik A Professional Association

20080157843 - Signal driver having selectable aggregate slew rate to compensate for varying process, voltage or temperature conditions: A signal driver having a selectable aggregate slew rate, a method of driving a signal driver and a signal driver incorporating the driver or the method. The driver includes plural partial drivers configured to output signals based on time constants established by corresponding plural time-delay networks associated therewith. The signal... Agent: Texas Instruments Incorporated

20080157844 - Time delay circuit: A time delay circuit includes an RC circuit with a resistor and a capacitor connected, and a switch. The switch includes a first terminal, a second terminal, and a control terminal for controlling conduction of the first and second terminals. The first terminal is connected to an end of the... Agent: Pce Industry, Inc. Att. Cheng-ju Chiang

20080157845 - Clock buffer circuit, semiconductor memory device and method for controlling an input thereof: The present invention relates to a semiconductor memory device having a clock buffer circuit which buffers an external clock to generate an internal clock, wherein the clock buffer circuit comprises a rising clock buffer which buffers an external clock to generate a rising internal clock corresponding to a rising edge... Agent: Ladas & Parry LLP

20080157846 - Dc offset calibration apparatus and method: A DC offset calibration apparatus is disclosed. The DC offset calibration apparatus includes an adjustment circuit and an offset calibration circuit. The adjustment circuit is utilized for receiving an input signal and an offset calibration signal, and for adjusting the input signal to generate an output signal according to the... Agent: North America Intellectual Property Corporation

20080157847 - Dc offset calibration apparatus and method for differential signals: A DC offset calibration apparatus includes a first adjustment unit, a first offset calibration circuit, a second adjustment unit, and a second offset calibration circuit. The first adjustment unit adjusts a first input signal to generate a first output signal according to a first offset calibration signal. The first offset... Agent: North America Intellectual Property Corporation

20080157848 - Level shifter for use between voltage domains: A level shifter circuit 28 has a first buffer circuit 30 and a second buffer circuit 32, 34. An intermediate signal generated by the first buffer circuit 30 is directly passed to the second buffer circuit 32, 34 to control output of one of its output signal levels. A feedback... Agent: Nixon & Vanderhye, Pc

20080157849 - Switching control circuit: A switching control circuit, controlling a transistor, of a voltage generating circuit generating an output voltage of a target level from an input voltage applied to the transistor, comprising: an error amplifier circuit outputting an error voltage obtained by amplifying an error between a voltage according to the output voltage... Agent: Socal Ip Law Group LLP

20080157850 - Compensating quantity-providing circuit, stress-compensating circuit, stress-compensated circuit, apparatus for providing a compensating quantity, method for providing a compensating quantity and ring oscillator: A compensating quantity-providing circuit includes a frequency signal generator having an output for a frequency signal the frequency of which depends on mechanical stress in a circuit, and a compensating quantity provider having an input for the frequency signal and an output for a compensating quantity which is based on... Agent: Slater & Matsil LLP

20080157851 - Electrically programmable fuse sense circuit: A design structure for electrically programmable fuse sense circuit having an electrically programmable fuse and a reference resistance. A first current source is coupled, through a first switch, to the electrically programmable fuse. A second current source is coupled, through a second switch, to the reference resistance. A precharge signal... Agent: Ibm Corporation Rochester Ip Law Dept. 917

20080157857 - Booster circuit: A charge pump type booster circuit generates a positive or negative boosted output voltage by switching booster paths one by one. This charge pump type booster circuit includes a plurality of booster paths, each of the plurality of booster paths including at least one booster capacitor, wherein a number of... Agent: Mcginn Intellectual Property Law Group, Pllc

20080157855 - Efficient voltage rail generation: A voltage reference generation circuit having switch pairs coupled to systematically commutate a flying capacitor among adjacent pairs of voltage rail outputs. The circuit requires only a single flying capacitor, N+1 switch pairs, and N storage capacitors, to generate N intermediate voltage references between VDD and GND. A signal generator... Agent: Townsend And Townsend And Crew, LLP

20080157856 - Internal voltage generation device: An internal voltage generation device is disclosed which includes an internal voltage generator operated in response to an enable signal, the internal voltage generator generating an internal voltage using a reference voltage, and a sub-voltage generator for driving an output terminal of the internal voltage generator to a predetermined voltage... Agent: Cooper & Dunham, LLP

20080157853 - Method for using a multiple polarity reversible charge pump circuit: A multiple polarity reversible charge pump circuit is disclosed which, in certain embodiments, may be configured to generate a positive voltage at times and may be reversed to generate a negative voltage at other times. Such a charge pump circuit is advantageous if both the positive and negative voltage are... Agent: Zagorin O'brien Graham LLP (023)

20080157854 - Multiple polarity reversible charge pump circuit: A multiple polarity reversible charge pump circuit is disclosed which, in certain embodiments, may be configured to generate a positive voltage at times and may be reversed to generate a negative voltage at other times. Such a charge pump circuit is advantageous if both the positive and negative voltage are... Agent: Zagorin O'brien Graham LLP (023)

20080157852 - Unified voltage generation apparatus with improved power efficiency: Unified voltage generation techniques for efficiently generating a plurality of operational voltages for use within an electronic device, such as a memory system (e.g., memory product) providing data storage, are disclosed. A voltage generation circuit can generate a regulated base output voltage. The voltage generation circuit can include one or... Agent: Technology & Innovation Law Group, Pc Attn: 1901

20080157858 - Design structure for implementing oxide leakage based voltage divider network for integrated circuit devices: A design structure embodied in a machine readable medium used in a design process includes a voltage divider device, including a double gate field effect transistor (FET) having a first gate and a second gate disposed at opposite sides of a body region; the first and second gates configured to... Agent: Cantor Colburn LLP-ibm Burlington

20080157859 - Unified voltage generation method with improved power efficiency: Unified voltage generation techniques for efficiently generating a plurality of operational voltages for use within an electronic device, such as a memory system (e.g., memory product) providing data storage, are disclosed. A voltage generation circuit can generate a regulated base output voltage. The voltage generation circuit can include one or... Agent: Technology & Innovation Law Group, Pc Attn: 1901

20080157860 - Internal voltage generation circuit for generating stable internal voltages withstanding varying external conditions: There is provided an internal voltage generation circuit generating an internal voltage used for a semiconductor memory device. The internal voltage generation circuit includes a current mirror type internal voltage detector generating a comparison voltage and comparing the comparison voltage with a reference voltage to output the comparison result as... Agent: Ladas & Parry LLP

20080157861 - Standard voltage generation circuit: A standard voltage generation circuit is provided with a function of automatically stopping charging when a standard voltage reaches a stable voltage point by rapidly charging a standard voltage stabilization capacitor during transition from a standby state to a normal operation state. The standard voltage generation circuit is also provided... Agent: Wenderoth, Lind & Ponack L.l.p.

20080157863 - Noise cancellation circuit, analog signal processing circuit, and electronic instrument: A cancellation signal generation section generates a cancellation signal which cancels an alternating-current component of a power supply terminal voltage of a digital signal processing circuit section, and a synthesis section synthesizes the generated cancellation signal and a power supply voltage of an analog signal processing circuit section to cancel... Agent: Global Ip Counselors, LLP

20080157862 - Noise cancellation circuit, electronic circuit, and noise cancellation signal generation method: A coil section detects undesirable radiation generated from a baseband process circuit section mounted at a specific position on a substrate, the coil section including a wire with a specific shape that is disposed at a position close to the baseband process circuit section, and a cancellation signal generation section... Agent: Global Ip Counselors, LLP

20080157864 - Filter circuit: The present invention addresses a need for reducing the power consumption in a baseband filter used in a front-end wireless receiver while providing the necessary linearity. In particular, relatively high linearity can be obtained with lower power consumption than has heretofore been the case. This is achieved in embodiments of... Agent: John Bruckner, P.c.

20080157866 - Capacitance multiplier circuit: An integrated circuit including a capacitance multiplier having reduced parasitics and injected noise compared to conventional multiplier methods. The integrated circuit includes a reference capacitor and a current mirror arrangement coupled to the reference capacitor. The current mirror arrangement, which includes a current gain factor N, varies the capacitance of... Agent: Smith Frohwein Tempel Greenlee Blaha Llc

20080157865 - Tunable capacitance multiplier circuit: An integrated circuit including a tunable capacitance multiplier. The integrated circuit includes a reference capacitor and a current source arrangement coupled in parallel to the reference capacitor. The current source arrangement can include a plurality of current sources that are switchably coupled to the reference capacitor in a manner that... Agent: Smith Frohwein Tempel Greenlee Blaha Llc