Miscellaneous active electrical nonlinear devices, circuits, and systems inventions 06/08

20080150588 - System and method of detecting a phase, a frequency and an arrival-time difference between signals: A system and method for detecting a phase and a frequency and an arrival-time difference between two signals (118 and 120) that minimizes delay and jitter, and has stable operation even when the two signals (118 and 120) are essentially identical. The system includes two single-ended charge-pump (188), phase-frequency detection... Agent: Synnestvedt Lechner & Woodbridge LLP

20080150589 - Systems and methods for multiple equation graphing: Various systems and methods for comparing signals are disclosed herein. For example, some embodiments of the present invention provide comparator circuits with programmable hysteresis. Such circuits include a comparator input circuit that receives two inputs to be compared. The comparator input circuit provides a first differential current output based at... Agent: Texas Instruments Incorporated

20080150590 - Track and hold circuit: A track and hold circuit is disclosed, including: a source follower coupled to a voltage supply; a MOS transistor with well structure, the MOS transistor having a gate terminal coupled to a gate terminal of the source follower, a drain terminal coupled to its body terminal and a source terminal... Agent: North America Intellectual Property Corporation

20080150591 - Method and apparatus for synchronizing multiple direct digital synthesizers (ddss) across multiple printed circuit assemblies (pcas): A radio frequency generating system comprises a synchronization board that receives an external clock signal from a clock source and generates multiple copies of the external clock signal. Each of a plurality of signal generation board receives a copy of the external clock signal from the synchronization board. Each signal... Agent: Davidson Berquist Jackson & Gowdey LLP

20080150593 - Power-on reset circuit: A circuit and a method generate a power-on reset signal having a leading part and a trailing part. The circuit includes a startup circuit generating the leading part of the power-on reset signal and a second circuit generating the trailing part of the power-on reset signal. The power-on reset circuit... Agent: Macronix C/o Haynes Beffel & Wolfeld LLP

20080150592 - Sequence circuit: A sequence circuit includes a switch circuit (30) and a control circuit (50). The switch circuit has an input terminal connected with a node (11) and an output terminal connected to a super I/O chip (10). The control circuit includes a first transistor (Q4) and a second transistor (Q5), the... Agent: Pce Industry, Inc. Att. Cheng-ju Chiang

20080150594 - Start-up circuit for supply independent biasing: A wireless device includes a supply independent bias circuit such as a bandgap current generator or a Proportional-To-Absolute-Temperature (PTAT) current generator. A start-up circuit that includes an amplifier and a Schmidt trigger to provide the desired start-up that avoids regulation to an undesired state.... Agent: Intel Corporation C/o Intellevate, Llc

20080150595 - Start-up reset circuit and related method: A start-up reset circuit includes a flip-flop and a clock signal generator. The clock signal generator generates a first clock signal and a second clock signal, wherein there is a phase difference between the first clock signal and the second clock signal. The flip-flop receives an operation voltage and has... Agent: North America Intellectual Property Corporation

20080150596 - Charge pump circuit: Disclosed herein are embodiments of a charge pump that can provide an output voltage with an output current that remains sufficiently constant over an operating range of the output voltage... Agent: Intel/blakely

20080150598 - Apparatus and method for controlling a delay- or phase- locked loop as a function of loop frequency: A method and circuitry for a Delay Locked Loop (DLL) or a phase Locked Loop (PLL) is disclosed, which improves the loop stability at high frequencies and allows maximum tracking bandwidth, regardless of process, voltage, or temperature variations. Central to the technique is to effectively operate the loop at a... Agent: Wong, Cabello, Lutsch, Rutherford & Brucculeri, L.l.p.

20080150597 - Apparatus and methods for controlling delay using a delay unit and a phase locked loop: An apparatus for controlling a delay includes a phase locked loop and a delay unit. The phase locked loop generates an oscillation signal having a frequency substantially identical to that of a reference signal. The delay unit includes a delay cell block that outputs delayed signals by delaying the reference... Agent: Myers Bigel Sibley & Sajovec

20080150599 - Method and apparatus for generating random jitter: Apparatuses and methods comprise a phase shifter, an adjustable capacitance configured to adjust a phase shift of said phase shifter, an arbitrary waveform generator configured to adjust the adjustable capacitance, and a pulse pattern generator coupled to the phase shifter, the phase shifter is configured to control the pulse pattern... Agent: Driggs, Hogg, Daugherty & Del Zoppo Co., L.p.a.

20080150601 - Clock duty changing apparatus: A clock duty changing apparatus changes a duty ratio of an input clock signal with nearly 50% duty ratio to a target value being externally supplied and outputs the input clock signal thereinafter as an output signal. The apparatus includes a duty regulation circuit and a duty correction circuit. The... Agent: Foley And Lardner LLP Suite 500

20080150600 - Electrical signal duty cycle modification: The duty cycle of a signal is modified by passing the signal through a plurality of inverting stages. The inverting stages each have bias circuitry to influence the input switching threshold of inverters. Multiple duty cycle modification circuits produce non-overlapping local oscillator signals in a system.... Agent: Lemoine Patent Services, Pllc

20080150602 - Apparatus, system, and method for hardened latch: Various embodiments include a latch having a node to receive input information, and a first pseudo-inverter with a first input node, a second input node, and an output node to generate output information based on information at the first and second input nodes. The latch may have a feedback circuit... Agent: Schwegman, Lundberg & Woessner, P.a.

20080150603 - Signal generation circuit, jitter injection circuit, semiconductor chip and test apparatus: There is provided a signal generation circuit for generating an output signal including jitter injected thereto. The signal generation circuit includes a jitter output section that outputs a first jitter signal and a second jitter signal which have different frequencies from each other, a carrier output section that outputs a... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

20080150604 - Converter having a time-delay circuit for pwm signals: A converter includes a time-delay circuit for a PWM signal, applied to input of the time-delay circuit, by which rising edges of the PWM signal are delayed by an ON delay and falling edges of the PWM signal are delayed by an OFF delay, in order to form a drive... Agent: Kenyon & Kenyon LLP

20080150605 - Clock distribution network architecture with clock skew management: Disclosed herein is a digital system that includes a distribution network having a path to carry a reference clock and an adjustable delay element disposed along the path, and first and second clock domains coupled to the distribution network to receive the reference clock and configured to be driven by... Agent: Lempia Braidwood Llc

20080150606 - Clock supplying apparatus: Disclosed herein is a clock supplying apparatus for supplying a clock to a digital circuit, including: a differential clock driver; a first clock line along which a first clock of a positive phase from the clock driver propagates; a second clock line along which a second clock of a reverse... Agent: Rader Fishman & Grauer Pllc

20080150607 - Device fand method for signal processing: An analog real-time signal processing device and method are presented. The device is configured to perform electrical signal processing. The device comprises an electronic circuit including at least one basic unit of electrodes, the basic unit being configured to be sensitive to an external field, such as input photon flux,... Agent: Browdy And Neimark, P.l.l.c. 624 Ninth Street, Nw

20080150608 - Integrated semiconductor circuit: An integrated semiconductor circuit is provided with a connection node, which is provided for decoupling electric signals, and with a plurality of electric signal lines, which are formed to provide in-circuit signals, particularly test signals, to the connection node. An in-circuit release device, which can be switched between a release... Agent: Muncy, Geissler, Olds & Lowe, Pllc

20080150609 - Operation and circuitry of a power conversion and control circuit: Since parallel MOSFETs are usually driven with one gate signal in power applications, the current sharing between the MOSFETs is automatically established with regard to the characteristics of the individual MOSFETs. This may lead to a large non-uniformity of the current distribution between the MOSFETs. According to the present invention,... Agent: Nxp, B.v. Nxp Intellectual Property Department

20080150610 - System and method for compensating for pvt variation effects on the delay line of a clock signal: The present invention is directed to a method for compensating for process, voltage, and temperature variation without complex online/offline swapping of data paths requiring a dedicated FIFO (First-in First-out) buffer design. Delay cells are trained for each clock path (namely a Functional delay) and a spare delay cell is trained.... Agent: Lsi Corporation

20080150611 - System for connecting a sensor to a controller: A sensor to controller connection system including a power source, a controller in communication with the power source, and a sensor in communication with the power source and the controller, the sensor including sensor electronics and a current source, the current source having a control input and an output, the... Agent: Delphi Technologies, Inc.

20080150612 - Switching circuit for cmos circuit: A controlling circuit for controlling on-off switching of a power supply for a CMOS circuit includes a CMOS circuit (20) and a switch (30). The CMOS circuit includes a first circuit (50) for storing the system time of the computer and a second circuit (70) for storing other system settings... Agent: Pce Industry, Inc. Att. Cheng-ju Chiang

20080150613 - Electrical fuse circuit: A gate of a MOS transistor connected to a fuse device in series is controlled by an AND circuit connected to the same power source as the fuse device is connected, thereby pulling down one input of the AND circuit to a ground. Thus, misprogramming of the fuse device when... Agent: Mcdermott Will & Emery LLP

20080150614 - Method and system for dynamic supply voltage biasing of integrated circuit blocks: A system and method are disclosed for using dynamic supply voltages to bias circuit blocks within integrated circuits. By considering current requirements for circuit blocks based upon process variations and environmental conditions, a dynamic supply voltage can be used such that operational integrity can be maintained while reducing power consumption.... Agent: O'keefe, Egan, Peterman & Enders LLP

20080150615 - System for providing a reference voltage to a semiconductor integrated circuit: A system for providing a reference voltage includes a tester adapted to provide a predetermined current, a first ground pad connected to a ground voltage of the tester, a second ground pad connected between the tester and the first ground pad, the second ground pad being connected to the tester... Agent: Lee & Morse, P.c.

20080150616 - Input/output circuit and input/output device: An input/output circuit has an output terminal, a first transistor, a second transistor, a pulse generator, and a bias circuit. The first transistor drives the output terminal based on a predetermined signal. The second transistor controls a potential of the gate of the first transistor. The pulse generator outputs a... Agent: Volentine & Whitt Pllc

20080150618 - Apparatus and method for generating internal voltage in semiconductor integrated circuit: An internal voltage generating apparatus includes: a voltage detector that detects the level of the internal voltage and outputs a fixed level detection signal and a variable level detection signal. An oscillation controller generates an oscillation enable signal according to whether the fixed level detection signal and the variable level... Agent: Venable LLP

20080150619 - Charge pump circuit and methods of operation thereof: A dual mode charge-pump circuit and associated method and apparatuses for providing a plurality of output voltages, using a single flying capacitor, the circuit including a network of switches that is operable in a number of different states and a controller for operating said switches in a sequence of the... Agent: Dickstein Shapiro LLP

20080150620 - Charge pump circuit and methods of operation thereof: A charge pump circuit, and associated method and apparatuses, for providing a split-rail voltage supply, the circuit having a network of switches that is operable in a number of different states and a controller for operating the switches in a sequence of said states so as to generate positive and... Agent: Dickstein Shapiro LLP

20080150621 - Charge pump circuit and methods of operation thereof: A charge pump circuit and associated method and apparatuses for providing a plurality of output voltages using a single flying capacitor. The circuit includes a network of switches that are operable in a number of different states and a controller for operating the switches in a sequence of states so... Agent: Dickstein Shapiro LLP

20080150622 - Semiconductor integrated circuit and method of controlling internal voltage of the same: A semiconductor integrated circuit comprising: a first voltage generator configured to generate a first voltage in response to activation of a first enable signal, wherein the first enable signal is generated by detecting a level of the first voltage; and a second voltage generator configured to generate a second voltage... Agent: Venable LLP

20080150617 - Voltage pump circuit with an oxide stress control mechanism for use in high-voltage applications in an integrated circuit: A voltage pump circuit that has an oxide stress control mechanism is disclosed. In particular, the oxide stress control mechanism of the voltage pump circuit ensures a safe transistor gate-to-source voltage in high-voltage applications in an integrated circuit. In particular, the down level of the gate voltage of the output... Agent: Downs Rachlin Martin Pllc

20080150623 - Voltage regulator integrated with semiconductor chip: The present invention reveals a semiconductor chip structure and its application circuit network, wherein the switching voltage regulator or converter is integrated with a semiconductor chip by chip fabrication methods, so that the semiconductor chip has the ability to regulate voltage within a specific voltage range. Therefore, when many electrical... Agent: Megica Corporation

20080150624 - Vgs replication apparatus, method, and system: A gate-to-source voltage (Vgs) replication circuit includes a diode-connected NMOS transistor coupled to a current source to draw a drain-to-source current therethrough. The generated Vgs is imposed across a source-to-gate junction of a PMOS transistor. A second PMOS transistor is coupled in series with the first PMOS transistor such that... Agent: Lemoine Patent Services, Pllc

20080150625 - Method and apparatus for signal peak-to-average ratio reduction: A method and apparatus taught herein reduce the peak-to-average ratio (PAR) of a complex-valued signal based on detecting peaks in the signal that are above a peak threshold, characterizing the detected peaks in Cartesian coordinates, generating cancellation pulses in Cartesian coordinates based on the detected peak characterizations. PAR reduction processing... Agent: Coats & Bennett, Pllc

20080150626 - Time variant filter with reduced settling time: A system includes an input for receiving an input signal, a filter having a changeable time constant, and a control circuit for changing the filter time constant in response to a property of the input signal.... Agent: Pietragallo Gordon Alfano Bosick & Raspanti, LLP

20080150627 - Circuit for suppressing voltage jitter and method thereof: A voltage jitter suppression circuit and a method thereof are disclosed. The circuit is utilized for alleviating the voltage jitter phenomenon of an IC. Regardless of the circuit frequency and voltage, the voltage jitter phenomenon of the circuit can be improved significantly by utilizing the present invention.... Agent: North America Intellectual Property Corporation

20080143391 - High speed latch comparators: In a latch circuit having a bistable pair of cross connected transistors of a first polarity and a third transistor of a second polarity, a current signal greater than a bias current is received at a latch circuit port, amplified with the third transistor, and applied to the latch circuit... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

20080143390 - Sense amplifier providing low capacitance with reduced resolution time: A sense amplifier circuit provides for high speed sensing with a high speed read operation, with a low capacitance and a low resolution time. The sense amplifier circuit includes a latch circuit having a first inverter circuit and a second inverter circuit cross coupled with each other. The amplifier circuit... Agent: Gardere Wynne Sewell LLP Intellectual Property Section

20080143392 - Envelope detector: An envelope detector operable to detect and record the minimum and maximum values present in a data stream. In various embodiments, the envelope detector includes a memory operable to store first and second data values, a first comparator, and a second comparator. The first comparator is generally operable to compare... Agent: Hovey Williams LLP

20080143393 - Output signal driving circuit and method thereof: The present invention provides an output signal driving circuit, which includes: a comparator coupled to a reference voltage for comparing the reference voltage and a voltage level of an output terminal to output a comparison signal; a first switch having a terminal coupled to a first supply voltage and having... Agent: North America Intellectual Property Corporation

20080143394 - Amplitude controlled sawtooth generator: A sawtooth voltage generator has a first capacitor that is charged with a variable feedback control current to provide a sawtooth output signal with a controlled amplitude. A feedback loop includes a comparator that compares a version of the sawtooth output signal with a fixed voltage reference to provide a... Agent: Schwegman, Lundberg & Woessner / Atmel

20080143395 - Method and device for managing a power supply power-on sequence: Apparatus, systems, and methods are disclosed that operate to trigger a reference voltage generator from a supply voltage detector, compare an output voltage level from the reference voltage generator with the a supply voltage, and to generate an enable signal when the supply voltage is greater than the output voltage... Agent: Schneck & Schneck

20080143396 - Semiconductor device: A data signal is generated in a pattern generation logic built in a TX port and given to a serializer, and a path is provided for looping an output of the serializer back to a deserializer and a CDR circuit of an RX port, whereby a BIST configuration enabling jitter... Agent: Mcdermott Will & Emery LLP

20080143400 - Dll circuit and method of controlling the same: A DLL circuit includes a buffer control unit configured to detect whether or not a DLL power supply exceeds a reference level and output a buffer control signal. A clock buffer buffers an external clock to generate an internal clock when the buffer control signal is enabled.... Agent: Venable LLP

20080143397 - Method and apparatus for removing the otter on clock signal: The present invention discloses a de-jittering method for a clock signal, which is implemented by adopting a controllable frequency divider and includes: taking the clock signal to be de-jittered as a reference signal, and comparing a feedback clock signal outputted by the controllable frequency divider with the reference signal; generating... Agent: Leydig Voit & Mayer, Ltd

20080143399 - Phase-locked loop circuit, delay locked loop circuit, timing generator, semiconductor test instrument, and semiconductor integrated circuit: A PLL and DLL are designed such that the power consumption can be reduced, the size can be easily reduced, the band of the locked loop can be a higher one, and the reliability can be improved. There are provided a phase comparator for measuring a feedback signal in synchronism... Agent: Yasuo Muramatsu Muramatsu & Associates

20080143398 - Pll circuit and design method thereof: A PLL circuit has an averaging device for averaging a rectangular wave signal output from a phase comparator at every period of a reference clock signal, and for outputting the average value. After the establishment of the phase synchronization of the PLL circuit, the average value of the averaging device... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20080143401 - Charge pump circuit: This invention offers a charge pump circuit that solves problems of deterioration of a device (a capacitive device or a charge transfer device) composing the charge pump circuit caused by leftover charges and malfunctioning due to the leftover charges. N-channel type charge transfer MOS transistors T0-TM, each of which has... Agent: Morrison & Foerster LLP

20080143404 - Delay locked loop circuit for semiconductor memory apparatus: A delay locked loop circuit for a semiconductor memory apparatus includes a duty cycle correcting part that corrects and outputs duty cycles of internal clocks. A clock pulse width detecting part detects a pulse width of an external clock and outputs a pulse width detecting signal. A driving part divides... Agent: Venable LLP

20080143403 - Digital delay locked loop: A digital delay locked loop including a plurality of controllable delay circuits connected in series, a phase detecting unit, and a delay control unit is disclosed. As an output end of each of the controllable delay circuits is coupled to the phase detecting unit, the phase detecting unit samples a... Agent: Jianq Chyun Intellectual Property Office

20080143402 - Digital pulse-width control apparatus: A digital pulse-width control apparatus including an input module, a digital delay locked loop, a plurality of programmable delay circuits connected in series, and a pulse-width modulation module is provided. The present invention uses the input module to vary a clock signal to reduce the limitation of a duty cycle... Agent: Jianq Chyun Intellectual Property Office

20080143405 - Process, voltage, temperature independent switched delay compensation scheme: A delay compensation circuit for a delay locked loop which includes a main delay line having a fine delay line comprising fine delay elements and a coarse delay line comprising coarse delay elements, the main delay line being controlled by a controller, the delay compensation circuit comprising: an adjustable fine... Agent: Borden Ladner Gervais LLP Anne Kinsman

20080143406 - Apparatus and method for adjusting slew rate in semiconductor memory device: A slew-rate adjusting apparatus for use in a semiconductor memory device includes: a slew-rate modulation signal generator for generating a slew-rate modulation signal according to the number of control codes having a first logic level among a plurality of control codes, which are programmable at an exterior; and a pre-driver... Agent: Mcdermott Will & Emery LLP

20080143407 - Signal generating circuit: Embodiments of a signal generating circuit are generally described herein. Other embodiments may be described and claimed.... Agent: Ked & Associates, LLP Intel Corporation

20080143408 - Pulse width modulator: In accordance with some embodiments, a pulse width modulator having a comparator with an applied adjustable waveform to generate a bit stream with a controllably adjustable duty cycle is provided.... Agent: Intel/blakely

20080143409 - Level shift circuit and control pulse shaping unit therewith: The present invention discloses a level shift circuit and a control pulse shaping unit therewith. A level shift circuit for transition of a low-voltage input signal into a high-voltage output signal, the circuit comprising two pairs of transistors and a control unit. Two pairs of transistors, wherein the transistors in... Agent: J C Patents, Inc.

20080143410 - Clock input/output device: A clock input/output device has three-state inverters Iv1 to Iv3 and an inverter Iv4, which cooperate to make equal the on-state resistance through a supply-voltage-side (VDD-side) transistor and the on-state resistance through a ground-voltage-side (0-side) transistor so as to make equal to VDD/2 the threshold voltage with reference to which... Agent: Fish & Richardson P.c.

20080143411 - Latched comparator and methods for using such: Various systems and methods for comparing signals are disclosed herein. For example, some embodiments of the present invention provide comparator circuits with a preamplifier circuit, a latch circuit and a current re-use circuit. The current re-use circuit applies a current to the preamplifier circuit during a transparent phase, and applies... Agent: Texas Instruments Incorporated

20080143412 - Semiconductor integrated circuit: In a dynamic flip-flop circuit with a data selection function, for example, when data having an H value has been selected using a selection signal S0, a first node N1 is L and a second node N2 of a second dynamic circuit 1B is H, so that an output signal... Agent: Mcdermott Will & Emery LLP

20080143413 - Programmable delay circuit: A programmable delay circuit including a first inverter, a second inverter, a variable resistance unit, and a variable capacitance unit is provided. The first inverter receives a positive-phase received signal, and transmits an anti-phase output signal through an anti-phase output signal line. The second inverter receives an anti-phase received signal,... Agent: Jianq Chyun Intellectual Property Office

20080143414 - Clock signal generator: A clock signal generator including: a signal generation unit that outputs a first clock signal composed of a single frequency component; and a phase angle detection unit that detects phase angles of the first clock signal by comparing a plurality of threshold values set within the amplitude of the first... Agent: Harness, Dickey & Pierce, P.L.C

20080143415 - Real time clock rate checker and recovery mechanism: A circuit, method, and system are disclosed. In one embodiment the circuit comprises a ring oscillator circuit having a plurality of delay elements, the ring oscillator circuit to generate a clock signal frequency, a checker circuit to compare a count of clock signal oscillations observed per complete loop of the... Agent: Intel Corporation C/o Intellevate, Llc

20080143416 - Clock distribution network, structure, and method for providing balanced loading in integrated circuit clock trees: A clock distribution network, structure, and method for providing balanced loading is disclosed. In particular, a clock distribution network may be formed of one or more clock fanout distribution levels. Each respective distribution level may include an equal number of buffer circuits and wiring routes that have substantially identical physical... Agent: Downs Rachlin Martin Pllc

20080143417 - Low latency, power-down safe level shifter: In one embodiment, an apparatus comprises a circuit supplied by a first supply voltage during use, the circuit having at least a first input signal; and a level shifter supplied by the first supply voltage during use and coupled to provide the first input signal to the circuit. The level... Agent: Meyertons, Hood, Kivlin, Kowert & Goetzel, P.c.

20080143419 - System for automatically selecting intermediate power supply voltages for intermediate level shifters: The present invention provides for a system comprising a level shifter configured to receive a first clock signal from a first power domain, to receive a counter signal, to select one of a plurality of intermediate voltages in response to the received counter signal, and to generate a second clock... Agent: Ibm Corporation (cs) C/o Carr LLP

20080143418 - Voltage level shifter with single well voltage: This invention discloses a voltage level shifter, which comprises a first P-type metal-oxide-semiconductor (PMOS) transistor having a gate, a source and a bulk coupled to an input terminal, a first positive voltage power supply and a second positive voltage power supply, respectively, and a second PMOS transistor having a source,... Agent: Howard Chen, Esq. Preston Gates & Ellis LLP

20080143420 - Internal voltage trimming circuit for use in a semiconductor memory device and method thereof: An internal power voltage trimming circuit and its method individually or simultaneously perform level trimming for a plurality of power voltages in a semiconductor memory device. The internal power voltage trimming circuit includes a trimming control signal generator for generating a trimming selection signal and a trimming enable signal by... Agent: Lowe Hauptman Ham & Berner, LLP

20080143421 - Bidirectional switch and method for driving bidirectional switch: A bidirectional switch comprises a first FET, a second FET, and a switch controller for controlling a conductive state in which current from a bidirectional power supply electrically connected to drain terminals bidirectionally flows, and a nonconductive state in which the current does not flow. In the conductive state, the... Agent: Mcdermott Will & Emery LLP

20080143422 - Trimming circuits and methods: The invention relates to techniques for programming trimming circuitry of a power integrated circuit without the need for separate programming pins. We describe a power supply controller IC with internal circuitry, a plurality of external connections, the IC further comprising trimming circuitry with no external connections to said IC other... Agent: Schwegman, Lundberg & Woessner, P.a.

20080143423 - Semiconductor integrated circuit and manufacturing method therefor: The present invention is directed to realize high manufacture yield and compensate variations in threshold voltage of a MOS transistor with small overhead. A semiconductor integrated circuit includes a CMOS circuit for processing an input signal in an active mode, a control switch, and a control memory. The control switch... Agent: Miles & Stockbridge Pc

20080143425 - Dc/dc converter and semiconductor device using dc/dc converter: It is an object to provide a DC/DC converter that can stabilize power supply potential in use. It is another object to provide a semiconductor device in which circuit operation is stabilized. In addition to a power supply that supplies potential to be reference potential of boosting in a DC/DC... Agent: Fish & Richardson P.c.

20080143424 - Dual edge modulated charge pumping circuit and method: Dual edge modulated charge pumping circuit has an output terminal, a charge pumping conversion circuit, and a dual edge modulated control circuit. The charge pumping conversion circuit has a first capacitor, a second capacitor, and a switch combination circuit. The second capacitor is coupled between the output terminal and a... Agent: North America Intellectual Property Corporation

20080143426 - Method for reducing leakage current of thin film transistor by applying static voltage: An exemplary method for reducing leakage current of thin film transistors (TFTs) of a TFT array substrate (200) includes: providing a TFT array substrate, the TFT array substrate including a number of gate lines, a number of data lines, and a number of TFTs, each TFT including a gate electrode,... Agent: Wei Te Chung Foxconn International, Inc.

20080143427 - Circuit and method for adjusting a voltage drop: An integrated circuit includes a circuit for adjusting a voltage drop. The circuit includes a reference voltage node, an output node and a driver circuit coupled between the reference voltage node and the output node. The driver circuit includes an impedance causing a current flow through the driver circuit when... Agent: Slater & Matsil LLP

20080143429 - Current driving device: A current driving device comprises: a voltage supply part; a current supply part; and a plurality of current output parts, each comprising a current-voltage converting function, a voltage-current converting function, and a voltage holding capacitance element. The current output part takes three operation modes. Under a voltage supply mode, the... Agent: Mcdermott Will & Emery LLP

20080143428 - Semiconductor integrated circuit: A high voltage reception terminal is formed in a semiconductor integrated circuit without increasing the number of manufacturing processes and the manufacturing cost. A transfer gate configured from a NMOS, which is the high withstand voltage transistor, and a pull-up resistor are formed. An input terminal of the transfer gate... Agent: Morrison & Foerster LLP

20080143430 - Output signal driving circuit and method of driving output signal: An output signal driving circuit is provided. The output signal driving circuit includes a first switch, a second switch, a third switch, and a fourth switch. The first switch is for selectively conducting a first supply voltage with a first terminal according to a first control signal. The second switch... Agent: North America Intellectual Property Corporation

20080143431 - Power gating techniques able to have data retention and variability immunity properties: A power gated semiconductor integrated circuit comprises: (1) logic circuit to be power gated, said logic circuit having a virtual ground rail; (2) footer device disposed between said virtual ground rail and a ground rail for reducing power consumption of said logic circuit; and (3) virtual rail voltage clamp disposed... Agent: Harrington & Smith, Pc

20080143432 - Active emc filter for machine tools: An active EMC filter for machine tools allows reducing the leakage current normally induced by large phase-to-ground capacitances. The filter may comprise an active shunt module or an impedance converter or a correction signal generator and is suitable both for three-phase and single-phase applications.... Agent: Blank Rome LLP

20080143433 - Active emc filter for medical applications: An active EMC filter for medical applications allows reducing the leakage current normally induced by large phase-to-ground capacitances. The filter may comprise an active shunt module or an impedance converter or a correction signal generator and is suitable both for three-phase and single-phase applications.... Agent: Blank Rome LLP

20080143434 - Transconductor: Disclosed is a transconductor including: first and second transistors each having first and second gates, the first and second gates being independently controlled, differential voltage input being supplied between the one first gate and the other first gate, the one source and the other source being connected, a first control... Agent: Amin, Turocy & Calvin, LLP

20080136456 - Sampling circuit and sampling method thereof: A sampling circuit includes a sampling unit, a first delay chain, an inverter, and a second delay chain. The sampling unit detects edge triggers of a first delayed signal and a second delayed signal for sampling input data to generate output data signal; the first delay chain is coupled to... Agent: North America Intellectual Property Corporation

20080136457 - Serial inteface circuit for a single logic input pin of an electronic system: A serial interface circuit for a single logic input pin of an electronic system, comprising a decoder for converting a pulse width modulated input signal applied to the pin to a sequence of logic low and logic high values. The decoder comprises an up/down counter with a count input connected... Agent: Texas Instruments Incorporated

20080136458 - Method and system for wide range amplitude detection: Aspects of a method and system for wide range amplitude detection are provided. In this regard, many electronic systems may require amplitude detection of a variety of signals with widely varying amplitudes. Aspects of the invention may comprise suitable logic, circuitry, and/or code to perform amplitude detection and may be... Agent: Mcandrews Held & Malloy, Ltd

20080136459 - Data amplifying circuit for semiconductor integrated circuit: A data amplifying circuit for a semiconductor integrated circuit including a controller configured to generate a control signal for adjusting an amplification step in response to a test signal, and a data amplifier configured to amplify an input signal one time or two or more times in response to the... Agent: Venable LLP

20080136460 - Comparator: A comparator has: an offset setting portion adapted to set an offset voltage; an offset subtracting portion adapted to subtract the offset voltage from a non-inverting input voltage; and a comparing portion adapted to shift the output logic level thereof according to which of the output voltage of the offset... Agent: Fish & Richardson P.c.

20080136461 - Comparator with reduced power consumption and method for the same: Techniques pertaining to a comparator circuit with reduced power consumption are disclosed. According to one aspect of the present invention, the comparator unit has a pair of input signal pins VIP and VIN, a pair of output signal pins VOR and VOS, and a clock signal pin CLK. In operation,... Agent: Silicon Valley Patent Agency

20080136462 - Apparatus and method of generating dbi signal in semiconductor integrated circuit: An apparatus for generating a DBI signal in a semiconductor integrated circuit includes a full adder that includes data input terminals and a carry input terminal, each of which receives data, performs an operation on the received data, thereby outputting a sum and a carry. A half adder includes data... Agent: Venable LLP

20080136463 - Method and system for an lc resonance current gain boosting amplifier: Aspects of a method and system for an integrated LC resonant current gain boosting amplifier may include amplifying within a chip, via an on-chip LC current gain circuit, an alternating current (AC) generated by an on-chip voltage-to-current converter, and converting within the chip, via an on-chip current-to-voltage circuit; the amplified... Agent: Mcandrews Held & Malloy, Ltd

20080136464 - Method of fabricating bipolar transistors and high-speed lvds driver with the bipolar transistors: Provided is a differential signal driver capable of operating at a high speed at a low voltage of 1.8V. The differential signal driver includes: a differential-signal driving circuit for switching input differential signals and outputting a common mode voltage through first and second output nodes; and a common-mode feedback circuit... Agent: Rabin & Berdo, Pc

20080136465 - Semiconductor integrated circuit: A semiconductor integrated circuit is disclosed, which includes a current output buffer circuit including a differential circuit, a variable impedance circuit, and a constant current source, wherein the current output buffer circuit is driven by a constant current supplied by the constant current source, an output impedance of the current... Agent: Amin, Turocy & Calvin, LLP

20080136466 - Semiconductor integrated circuit driving external fet and power supply incorporating the same: A semiconductor integrated circuit includes: a switching control circuit having a first transistor and a second transistor coupled to an FET, and turning on and off the FET by turning on and off each of the first transistor and the second transistor, the FET attaining an OFF state when the... Agent: Fish & Richardson P.c.

20080136467 - Buffer chain driver: A buffer chain driver has two similar signal paths formed by series-connected buffer cells, each comprising two series connected inverter stages in each signal path. The output of the first inverter stage in each signal path is coupled to the output of the last inverter stage in the other signal... Agent: Texas Instruments Incorporated

20080136468 - Method and system for doubling phase-frequency detector comparison frequency for a fractional-n pll: Aspects of a method and system for signal processing are disclosed and may include using a frequency doubler to double the frequency of a reference signal utilized by a phase-frequency detector (PFD) in a fractional-N phase-locked-loop (PLL) synthesizer. Detecting and correcting a digital reference signal connected to the input of... Agent: Mcandrews Held & Malloy, Ltd

20080136469 - Semiconductor integrated circuit device and internal power control system including the same: One object of the present invention is to provide an LSI that can dynamically perform appropriate adjustment for a power voltage to be supplied to an internal circuit, not only at the time of the occurrence of the initial change of a performance due to a variation or variety factors... Agent: Ibm Microelectronics Intellectual Property Law

20080136470 - Method and circuit for rapid alignment of signals: Circuits and methods for aligning two or more signals including a first and second signal. In one embodiment, a shift register generates two or more shifted copies of the second signal, and each of a plurality of phase detectors receives the first signal and one of the shifted copies of... Agent: Brownstein Hyatt Farber Schreck, Pc

20080136473 - Filter circuit arrangement: A filter circuit arrangement for filtering of a radio-frequency signal has a first tunable filter and a phase regulation loop in order to hold the first tunable filter to a transmission phase constant relative to the frequency of the radio-frequency signal. The filter circuit arrangement has a second tunable filter... Agent: Schiff Hardin, LLP Patent Department

20080136471 - Generating an output signal with a frequency that is a non-integer fraction of an input signal: Generating an output signal having a frequency of 1/(M+F) of the frequency of the input signal, wherein M represents an integer and F represents a non-zero fraction. Assuming F equals (Q/R) in one embodiment, wherein Q and R are integers, R intermediate signals phase shifted by equal degree (relative to... Agent: Texas Instruments Incorporated

20080136474 - Pll circuit: A phase locked loop (PLL) circuit including a phase comparator for comparing a phase of a reference signal with a phase of a feedback signal, an oscillator for outputting an output signal at a frequency in accordance with an output of the phase comparator, a feedback loop for returning the... Agent: Arent Fox LLP

20080136472 - Power supply circuit for a phase-locked loop: A power supply circuit includes a first voltage regulator to generate a first supply voltage for a first circuit of a phase-locked loop and a second voltage regulator to generate a second supply voltage for a second circuit of the phase-locked loop. The first and second supply voltages are independently... Agent: Ked & Associates, LLP Intel Corporation

20080136478 - Apparatus and method of controlling operation frequency in dll circuit: A frequency multiplier increases the frequency of an external clock and outputs a high-frequency external clock. A period determinator determines whether or not a predetermined period of the external clock elapses and outputs a period determination signal. A frequency selector selectively transmits the external clock or the high-frequency external clock... Agent: Venable LLP

20080136475 - Control of a variable delay line using line entry point to modify line power supply voltage: Disclosed herein is a VDL/DLL architecture in which the power supply to the VDL, VccVDL, is regulated at least as a function of the entry point of the input signal (ClkIn) into the VDL. Specifically, VccVDL is regulated to be higher when the delay through the VDL is relatively small... Agent: Wong, Cabello, Lutsch, Rutherford & Brucculeri, L.l.p.

20080136477 - Delay apparatus for delay locked loop: A delay apparatus for a delay locked loop includes a plurality of delay devices that are formed by modeling a plurality of signal processing structures through which a delay locked loop clock output from a delay locked loop reaches an output circuit of a semiconductor memory apparatus from an output... Agent: Venable LLP

20080136476 - Delay locked loop: A semiconductor memory device includes a delay locked loop for achieving a delay locked state by correcting a phase difference between a reference clock and an internal delayed clock and for indicating the state that a larger delay amount than a maximum delay amount of a delay line is required,... Agent: Blakely Sokoloff Taylor & Zafman

20080136479 - Semiconductor memory device capable of easily performing delay locking operation under high frequency system clock: A semiconductor memory device includes a first clock buffer for outputting a first internal clock signal in response to an inverted signal of the system clock signal and for correcting a duty cycle ratio of the first internal clock signal in response to a control signal; a second clock buffer... Agent: Blakely Sokoloff Taylor & Zafman

20080136480 - Extracting a maximum pulse width of a pulse width limiter: An apparatus for extracting a maximum pulse width of a pulse width limiter is provided. The apparatus performs such extraction using a circuit that is configured to eliminate a majority of delay cells. The elimination of delay cells is made possible by replacing an OR gate in the circuit configuration... Agent: Ibm Corp. (wip) C/o Walder Intellectual Property Law, P.c.

20080136481 - Edge-triggered flip-flop design: An edge triggered flip-flop circuit is disclosed with a clock signal, an input signal, a switch module using the clock signal for defining a data passing window, and a latch module for receiving the input signal during the data passing window.... Agent: Duane Morris LLP Ip Department (tsmc)

20080136482 - Latch: A latch includes: an amplifying circuit, for receiving a first bias current in a first state for amplifying an input signal to generate an amplified signal; a latching unit, for latching the amplified signal and receiving a second bias current in a second state to output the amplified signal; and... Agent: Joe Mckinney Muncy

20080136483 - Latch circuit: A latch circuit (1) comprising, a differential input with an inverting input (D+) and a non-inverting input (D−). The latch further comprises a differential output with an inverting output (Q+) and a non-inverting output (Q−). One of the outputs (Q−) is coupled to one of the inputs input (D+) having... Agent: Nxp, B.v. Nxp Intellectual Property Department

20080136484 - Sense amplifier control signal generating circuit of semiconductor memory apparatus: A sense amplifier control signal generating circuit of a semiconductor memory apparatus is provided. The sense amplifier control signal generating circuit includes a timing control unit that models a transmission path of data from a memory cell to a sense amplifier through a bit line and generates a timing control... Agent: Venable LLP

20080136485 - Delay circuit and delay synchronization loop device: A delay circuit includes a first delay line circuit having a plurality of stages of delay units, a second delay line circuit having a plurality of stages of delay units, a plurality of transfer circuits provided in association with respective stages of the delay units of the first delay line... Agent: Sughrue Mion, Pllc

20080136486 - Circuit for generating clock of semiconductor memory apparatus: A circuit for generating a clock of a semiconductor memory apparatus. A reference voltage generator is configured to generate a reference voltage. A reference current generator is configured to generate a reference current that has a constant current value regardless of a change in temperature. An oscillator is configured to... Agent: Venable LLP

20080136487 - Boost circuit and level shifter: A level shifter including a first boost circuit, an inverter, a second boost circuit and a level shift circuit is disclosed. The first boost circuit receives an input signal, and a first amplification factor for the input signal is determined based on a control signal. The inverter receives the input... Agent: Joe Mckinney Muncy

20080136488 - Drive circuit with bot level shifter for transmitting an input signal and assigned method: A drive circuit in power electronic systems comprising a half-bridge circuit of two power switches, a first so-called TOP switch and a second so-called BOT switch, which are arranged in a series circuit. The drive circuit has a BOT level shifter for transmitting an input signal from a drive logic... Agent: Cohen, Pontani, Lieberman & Pavane

20080136489 - Level shifter: In a level shifter, OFF leakage currents flow through two N-type transistors for signal input even when they are OFF. However, another N-type transistor serving as an OFF leakage generation circuit and three P-type transistors serving as current mirrors, which constitute a current conversion circuit, supply to the signal-input transistors... Agent: Mcdermott Will & Emery LLP

20080136490 - Voltage integrator and transformer provided with such an integrator: A voltage integrator, comprising a resistor (4) and a capacitor (5) connected in series between an input voltage (V) and ground, wherein the resistance (R) of said resistor and the capacitance (C) of said capacitor are adapted such that a voltage (Vc) across said capacitor approximates the integral of said... Agent: Philips Intellectual Property & Standards

20080136491 - Square cell having wide dynamic range and power detector implementing same: A square cell comprises first and second bipolar transistors each having an emitter, collector and base, the bases of the transistors being connected for receiving an input voltage, and first and second resistors in series with the first and second bipolar transistors respectively and with a source of reference voltage.... Agent: Mcdermott Will & Emery LLP

20080136492 - Leakage compensation circuit using limiting current inverter: The leakage compensation circuit includes: a replica circuit of a circuit to be compensated, the replica circuit provides a replica leakage current equal to a leakage current of the circuit to be compensated; an amplifier having a first input coupled to the replica circuit and a second input coupled to... Agent: Texas Instruments Incorporated

20080136493 - Electronic device and communication device comprising the same: In an electronic device according to the present invention, a source of the first signal-wire drive transistor is connected to a first power supply, a drain of the first signal-wire drive transistor is connected to a signal wire, and a control circuit controls a gate voltage so that a current... Agent: Mcdermott Will & Emery LLP

20080136494 - Switching circuit, switching module and method of controlling the switching circuit: A switching circuit includes switching transistors connected to one of an input terminal and an output terminal of the switching circuit, and a control bias supply circuit that supplies a control bias for cutting off all the switching transistors to the switching transistors when all of the switching transistors are... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20080136495 - Transistor switch: A circuit is disclosed, including a transistor switch having a first terminal to receive an input voltage, a second terminal to output an output voltage and a gate terminal; a determination circuit, coupled to the first terminal and the second terminal of the transistor switch, to determine a lower or... Agent: Brinks Hofer Gilson & Lione/infineon Infineon

20080136496 - Novel fuse programming schemes for robust yield: An embodiment of the present invention is a technique to program a fuse. A program circuit generates first and second currents to program the fuse. The second current is higher than the first current. A control circuit controls generating the first and second currents in succession.... Agent: Intel/blakely

20080136498 - Method and system for buffering a clock signal: A method and system for buffering a clock signal is provided. The method may include self-biasing a PMOS transistor of a buffer, utilized for amplifying an in-phase/quadrature phase signal, to produce a first bias voltage at the gate of a PMOS transistor, and biasing an NMOS transistor of the buffer... Agent: Mcandrews Held & Malloy, Ltd

20080136499 - Selective coupling of voltage feeds for body bias voltage in an integrated circuit device: An integrated circuit device having a body bias voltage mechanism. The integrated circuit comprises a resistive structure disposed therein for selectively coupling either an external body bias voltage or a power supply voltage to biasing wells. A first pad for coupling with a first externally disposed pin can optionally be... Agent: Murabito, Hao & Barnes LLP

20080136497 - Tunable voltage controller for a sub-circuit and method of operating the same: The present invention provides a tunable voltage controller for use with a sub-circuit. In one embodiment, the tunable voltage controller includes a diode-connected MOS transistor contained in a doped well of a substrate and configured to provide a voltage for the sub-circuit. Additionally, the tunable voltage controller also includes a... Agent: Texas Instruments Incorporated

20080136500 - Charge pump for generation of multiple output-voltage levels: A charge pump circuit for generating a plurality of voltages in excess of a supply voltage includes a first group of cascaded charge-pump stages, the input of a first charge pump stage in the first group being driven from the supply voltage. A first output stage has an input driven... Agent: Schwegman, Lundberg & Woessner / Atmel

20080136502 - Semiconductor integrated circuit: In order to provide a semiconductor IC unit such as a microprocessor, etc., which satisfies both fast operation and lower power consumption properties with its high quality kept, the semiconductor IC unit of the present invention is composed so as to include a main circuit (LOG) provided with transistors, which... Agent: Kenyon & Kenyon LLP

20080136501 - Voltage generating circuit and semiconductor memory device with the same: A voltage generating circuit includes: a pumping circuit configured to boost a power supply voltage in accordance with a charge transfer operation; a voltage detection circuit configured to detect the output voltage of the pumping circuit; a first pumping control circuit configured to control the pumping circuit in accordance with... Agent: Oblon, Spivak, Mcclelland Maier & Neustadt, P.c.

20080136503 - Method and system for a process sensor to compensate soc parameters in the presence of ic process manufacturing variations: Certain aspects of a method and system for a process sensor to compensate SoC parameters in the presence of IC process manufacturing variations are disclosed. Aspects of one method may include determining an amount of process variation associated with at least one transistor within a single integrated circuit. The determined... Agent: Mcandrews Held & Malloy, Ltd

20080136504 - Low-voltage band-gap reference voltage bias circuit: A low-voltage band-gap reference voltage bias circuit according to the present invention can provide a stable reference voltage at a supply voltage of about 1V or lower irrespective of a power supply voltage or temperature variation by flowing a PTAT mirror current into diodes and resistors and obtaining the average... Agent: Ladas & Parry LLP

20080136505 - Integrated circuit with standby mode minimizing current consumption: The invention relates to electronic integrated circuits capable of operating either in active mode or in standby mode and to have, in standby mode, a very low current consumption. According to the invention, the leakage current of a power transistor inserted in series between a supply terminal and an active... Agent: Lowe Hauptman & Berner, LLP

20080136506 - Output circuit for a bus: An output circuit for a bus whose output node is connected to a bus, including a first current source connected to a first reference potential, a first semiconductor switching element connected between the first current source and the output node, a current control circuit for controlling the first semiconductor switching... Agent: Rader Fishman & Grauer Pllc

20080136507 - Analog phase control circuit and method: In some embodiments, an array of sleep transistors is provided, wherein a combination of said transistors may be enabled during an active mode to reduce leakage depending on the leakage characteristics of a chip or associated chip.... Agent: Intel/blakely

20080136508 - Semiconductor integrated circuit device: A semiconductor integrated circuit device for fast and low power operations, comprising a plurality of circuit blocks of a chip, each of which has a plurality of states with different power consumption values. A power management circuit determines the state of each of the circuit blocks so as not to... Agent: Reed Smith LLP

20080136509 - Audio filter using a diode connected mosfet: A diode connected P-type CMOS transistor is operated in the sub-threshold area and, with a bypass capacitor, operates as a low pass audio filter. The equivalent resistance of the CMOS transistor in the sub-threshold range is very high—in the gigaOhm range. With this size resistor, a capacitor in the 1-25... Agent: Cesari And Mckenna, LLP

20080129344 - Phase-difference detecting apparatus and method: A phase-difference detecting method is for detecting phase difference between a first signal and a second signal of the same frequency. First, generate a detection signal. Next, sample the detection signal respectively according to the first signal and the second signal to obtain a first sample value and a second... Agent: Rabin & Berdo, Pc

20080129343 - Static phase adjust using lc tanks with offset center frequencies: A phase detector includes a first clock driver comprising a first LC tank. The first clock driver provides a strobe to a plurality of flip-flops associated with sampled data being received by the phase detector. The second clock driver includes a second LC tank. The second clock driver provides a... Agent: Gauthier & Connors, LLP

20080129345 - Low-voltage, low-power-consumption, and high-speed differential current-sense amplification: A differential current-sensing amplifier includes two inverters, two resistors, and three switches. The first inverter has a first output and the second inverter has a second output. The first resistor is connected between the first inverter and ground, and the second resistor is connected between the second inverter and ground.... Agent: Law Offices Of Michael Dryja

20080129346 - Automatic self-adaptive keeper system with current sensor for real-time/online compensation for leakage current variations: A device and method for automatically detecting and optimally compensating die leakage current under a wide range of leakage conditions. A variable or reconfigurable (self-adaptive) keeper tracks current leakage online (in real time). The control input to the keeper is coupled to a leakage current sensor, which is in turn... Agent: Dillon & Yudell LLP

20080129348 - High performance low power multiple-level-switching output drivers: Long existing performance, noise, and power consumption problems of prior art output drivers are solved by using n-channel transistors as pull up transistors and/or p-channel transistors as pull down transistors for high performance output drivers. Output drivers of the present invention can be fully compatible with HSTL, SSTL, LVDS, MIPI,... Agent: Jeng-jye Shau

20080129347 - Methods and systems for driving a load: In one embodiment, a circuit can selectively adjust a current for driving a load. The circuit includes a sensor configured to measure a magnetic field associated with the current and provide a sensor voltage representative thereof. A control circuit is configured to selectively adjust the current as a function of... Agent: Eschweiler & Associates Llc

20080129349 - Output slew rate control in low voltage differential signal (lvds) driver: A differential signal driver includes a pre-driver configured to generate a constant charging current and a constant discharging current. A first capacitor of the pre-driver is charged with the charging current when a differential input signal has a first state, and discharged with the discharging current when the differential input... Agent: Bever, Hoffman & Harms, LLP

20080129350 - Frequency band extending apparatus, frequency band extending method, player apparatus, playing method, program and recording medium: A player apparatus for playing an input signal after band-extending the input signal includes: an extension controller to determine an extension start band for the input signal in accordance with information relating to the input signal; and a band divider to divide the input signal into a plurality of sub-band... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20080129351 - Spread spectrum clock generation: The present disclosure provides a spread spectrum clock generation system having a digitally controlled phase locked loop (PLL) and a digital frequency profile generator to create a near optimal frequency modulation profile for the purpose of achieving spectral flatness in the output frequency modulated clock. The circuit is combined with... Agent: Docket Clerk

20080129352 - Linear phase frequency detector and charge pump for phase-locked loop: Techniques for achieving linear operation for a phase frequency detector and a charge pump in a phase-locked loop (PLL) are described. The phase frequency detector receives a reference signal and a clock signal, generates first and second signals based on the reference and clock signals, and resets the first and... Agent: Qualcomm Incorporated

20080129353 - Phase locked loop with small size and improved performance: A phase locked loop (PLL) with small size and improved performance is achieved using a type 1 PLL, a frequency detector and logic for switching between the type 1 PLL and frequency detector. The logic disables the type 1 PLL and enables the frequency detector to bring the frequency of... Agent: Garlick Harrison & Markison

20080129354 - Fast measurement initialization for memory: Systems and methods for synchronization of clock signals are disclosed. In a feedback system such as a delay-lock loop circuit, delays to be applied can be determined adaptively based on a phase difference between a reference signal and a clock signal being delayed. Such adaptive decisions can be made during... Agent: Knobbe Martens Olson & Bear LLP

20080129355 - Floating dc-offset circuit for phase detector: A floating DC-offset circuit for a phase detector. The circuit may provide a floating DC-offset to the phase detector, or to the voltage-controlled oscillator of the phase-locked loop. The circuit includes a voltage comparator, a clock, a digital resistor, and an offset line to a DC-offset branch of the phase... Agent: Bereskin And Parr

20080129357 - Adaptive integrated circuit clock skew correction: Apparatus for correcting clock skew in a circuit including at least one sequential circuit element and a clock generator operatively coupled to the sequential circuit element includes at least one programmable delay element connected in series with a data input and/or a clock input of the sequential circuit element. The... Agent: Ryan, Mason & Lewis, LLP

20080129356 - Cml delay cell with linear rail-to-rail tuning range and constant output swing: A current mode logic (CML) delay cell with linear rail-to-rail tuning range and constant output swing. The CML delay cell can include a tuning voltage input on a first and second transistor, contributing to a CML delay cell load, and a bias voltage input on a third transistor, as a... Agent: Cantor Colburn LLP - Ibm Research Triangle Park

20080129358 - Duty detection circuit: A duty detection circuit includes an integration circuit for receiving an RCLK signal and an FCLK signal that are internal clock signals generated by a DLL circuit, and generating voltage levels in accordance with the duty ratio of these internal clock signals; an amplifier for amplifying the output of the... Agent: Mcdermott Will & Emery LLP

20080129359 - Low-power clock gating circuit: Provided is a low-power clock gating circuit using a Multi-Threshold CMOS (MTCMOS) technique. The low-power clock gating circuit includes a latch circuit of an input stage and an AND gate circuit of an output stage, in which power consumption caused by leakage current in the clock gating circuit is reduced... Agent: Ladas & Parry LLP

20080129360 - Clock generator with programmable non-overlapping-clock-edge capability: A system and method for generating and optimizing clock signals with non-overlapping edges on a chip using a unique programmable on-chip clock generator. Overlapping of the edges of the clocking signals is avoided by adjusting an amount of delay introduced in the on-chip clock generator circuit. The amount of delay... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

20080129361 - Method and system for programmable delays on transport outputs: Methods and systems for controlling signals in a chip are described herein. Aspects of the invention may include receiving an input signal from a chip core and delaying the input signal utilizing a delay circuit prior to transmitting the input signal to an output port. The delay circuit may comprise... Agent: Mcandrews Held & Malloy, Ltd

20080129362 - Semiconductor device and method of designing semiconductor device: A semiconductor device designing method of the present invention corresponds to a method for designing a clock synthesization type semiconductor device, which is comprised of: a rough CTS (clock tree synthesis) step for performing the CTS within an adjustable range in multiple phases; a timing check step for judging whether... Agent: Mcdermott Will & Emery LLP

20080129363 - Semiconductor device: A semiconductor device receives differential input signals, performs predetermined signal processing, and outputs differential output signals. Plural rear surface electrodes, disposed in an m-row, n-column (m and n being integers) matrix form, on a rear surface of the semiconductor device, are formed. The rear surface electrodes for the differential input... Agent: Cantor Colburn, LLP

20080129364 - Dead band reduction in electronically controlled valves: An apparatus includes dead band reduction circuitry. The dead band reduction circuitry includes an input configured to receive an input signal and an output configured to provide an output signal. The dead band circuitry is configured to apply compensation to the input signal to create the output signal. The output... Agent: Harrington & Smith, Pc

20080129365 - Level shift circuit with low-voltage input stage: A level shift circuit with a low-voltage input stage, converting an input signal to an output signal, includes at least one level shift unit. The level shift unit includes a first transistor receiving a supply voltage and a first gate control signal to generate a second gate control signal, a... Agent: Wpat, Pc Intellectual Property Attorneys

20080129366 - Systems including level shifter having voltage distributor: An exemplary embodiment of such a system comprises: a level shifter includes a voltage distributor for receiving an input signal and respectively outputting a first signal and a second signal at a first node and a second node according to the input signal; and an output circuit coupled to the... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20080129367 - Method and apparatus for smart signal averaging: A method, apparatus, and computer usable program code for signal-to-noise enhancement. In one illustrative embodiment, a system is provided for signal-to-noise enhancement. The system includes a rank order filter and a comparator. The comparator receives an ordered set of data values from the rank order filter. A signal averager averages... Agent: Duke W. Yee

20080129368 - Superconducting single flux quantum modulator circuit: Objects of the present invention are to provide an integration circuit which produces no integration leak so that the bit accuracy is improved in a sigma-delta modulation circuit or a delta modulator circuit, which is based on a single flux quantum circuit that uses a flux quantum as an information... Agent: Stanley P. Fisher Reed Smith LLP

20080129369 - Current multiplexing circuit for optical power monitoring: The invention provides a current multiplexing circuit for time-domain multiplexing a plurality of current signals such as photocurrents that are received in a plurality of input terminals. The current signals are multiplexed using one or more analog low-resistance switches operational to connect each of the input terminals to an output... Agent: Teitelbaum & Maclean

20080129370 - Control circuit and method for a switching amplifier: In a control circuit and method for a high efficiency and low EMI switching amplifier, an input signal is compared with a reference signal to generate a comparison signal, and a control signal is generated in response to the comparison signal for a driver to generate an output signal. The... Agent: Rosenberg, Klein & Lee

20080129371 - Semiconductor device and trimming method: A device and method for determining target values for a parameter of a semiconductor device to be trimmed. A first target value is determined for a parameter to be trimmed for a first temperature, and a second target value differing from the first target value is determined for the parameter... Agent: Dicke, Billig & Czaja

20080129372 - Charge pump circuit and method therefor: In one embodiment, a charge pump circuit is used to keep a boost capacitor of a power supply system charged while the switch transistors are not switching such as when the power supply system is operating in a burst mode of operation.... Agent: Mr. Jerry Chruma Semiconductor Components Industries, L.l.c.

20080129373 - Voltage supplier of semiconductor memory device: The present invention provides voltage supplier for supplying an internal voltage with optimized drivability required for internal operation. The voltage supplier of a semiconductor memory device includes: an internal voltage detection means for detecting a voltage level of an internal voltage; a clock oscillation means for outputting a charge pumping... Agent: Mcdermott Will & Emery LLP