Miscellaneous active electrical nonlinear devices, circuits, and systems inventions 08/07

20070200600 - Bulk voltage level detector for semiconductor memory apparatus: A bulk voltage (VBB) level sensor for a semiconductor memory apparatus is disclosed. The VBB level detector includes a reference voltage generator for generating a first reference voltage of which level varies with temperature, a reference voltage comparator for receiving a second reference voltage and the first reference voltage to... Agent: Venable LLP

20070200599 - Detector of differential threshold voltage: A differential threshold voltage level detection circuit receives a differential voltage pair as an input, applying each component of the differential pair to an individual voltage shifting circuit. Each voltage shifting circuit is configured with a regulated current producing a shifted and a non-shifted version in-phase. For a shifted set... Agent: Schneck & Schneck

20070200601 - Differential drive circuit and method for generating an a.c. differential drive signal: The differential drive circuit generates a differential drive signal having a root mean square value defined by a digital input value. The differential drive signal includes a first differential component and a second differential component. The circuit comprises a first differential component generator and a second differential component generator. The... Agent: Kathy Manke Avago Technologies Limited

20070200602 - Drive circuit for power semiconductor switching device: A gate driving circuit for a voltage-driven power semiconductor switching device has (a) the voltage-driven power semiconductor switching device, (b) a driving circuit for supplying a drive signal to the gate electrode of the switching device, and (c) an inductance between the emitter control terminal or source control terminal of... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070200603 - Regulated adaptive-bandwidth pll/dll using self-biasing current from a vco/vcdl: A PLL/DLL circuit is current self-biased responsive to a current Ild provided from a voltage regulator to a VCO or VCDL. Bias current Ibias, which is proportional to Ild, is provided to components of the PLL/DLL, such as a charge pump or loop resistor, from an interconnect coupled to the... Agent: Deniro/rambus

20070200604 - Delay locked loop apparatus: The present invention relates to a delay locked loop (DLL) apparatus. The DLL apparatus includes: a first delay means converting a reference clock into a rising clock; a second delay means converting the reference clock into a falling clock by delaying the reference clock; a replica delay unit replica-delaying the... Agent: Ladas & Parry LLP

20070200605 - Dual operational mode cml latch: A dual purpose current mode logic (“CML”) latch circuit is provided which includes a CML latch operable to receive at least a pair of differential input data signals and at least one clock signal. The CML latch is operable to generate at least one output signal in accordance with the... Agent: International Business Machines Corporation Dept. 18g

20070200606 - Pulsed flip-flop and method of controlling the same: A pulsed flip-flop capable of adjusting a pulse width according to an operating voltage includes: a flip-flop operating in synchronization with a pulse signal; a pulse generating circuit generating the pulse signal in response to a clock signal; and a pulse width control circuit reducing a width of the pulse... Agent: F. Chau & Associates, LLC

20070200607 - Three-phase voltage-fed ac/dc converter: A three-phase voltage-fed AC/DC converter includes a conversion circuit which converts power from a DC voltage source to three-phase AC power. The converter further includes a UM conversion circuit which carries out dq conversion of the three-phase output voltage, a superior voltage control circuit which outputs a voltage reference vector... Agent: Darby & Darby P.C.

20070200608 - Self-timed thermally-aware circuits and methods of use thereof: Apparatus and methods for regulating gate delays of synchronous and asynchronous digital circuits. Thermally-sensitive circuits include, generally, temperature sensitive voltage sources outputting a voltage signal indicative of the temperature of the digital circuit, where the voltage signal reflects non-linear temperature sensitivity above a predetermined threshold temperature, and delay mechanisms receiving... Agent: Burns & Levinson, LLP

20070200609 - Integrated circuit devices generating a plurality of drowsy clock signals having different phases: An integrated circuit device which internally generates a plurality of drowsy clock signals having different phases is provided. The integrated circuit device includes a phase synchronizer configured to output a plurality of clock signals having different phases in response to an external clock signal and a drowsy clock signal output... Agent: Harness, Dickey & Pierce, P.L.C

20070200610 - Switched-mode power supply regulation: The invention concerns a circuit for detecting an overload in a load supplied by a switched-mode power supply, comprising: a first comparator of a first voltage based on the supply voltage of the load relative to a first threshold, supplying a regulating signal to a pulse generator controlling the switched-mode... Agent: Seed Intellectual Property Law Group PLLC

20070200611 - Dram boosted voltage supply: A circuit for providing an output voltage for a DRAM word line which can be used to drive memory word lines which can be as high as 2Vdd. Transistors in a boosting circuit are fully switched, eliminating reduction of the boosting voltage by Vtn through the transistors. The boosting capacitors... Agent: Hamilton, Brook, Smith & Reynolds, P.C.

20070200612 - Power supply apparatus and method: The apparatus may include a non-pumping power supply unit configured to generate a supply voltage from a power source voltage and/or configured to output the supply voltage. The apparatus may include a pumping power supply unit and/or a control circuit. The pumping power supply unit may be configured to generate... Agent: Harness, Dickey & Pierce, P.L.C

20070200614 - Apparatus and method reducing glitch in switching device: Provided are an apparatus and method of reducing a glitch in a switching device. The apparatus includes a latch latching a digital input signal and providing a digital output signal, a switching device segment unit including at least two switching device segment units, each one of the at least two... Agent: Volentine & Whitt PLLC

20070200613 - Gate driver circuit for switching device: A gate driver circuit of a voltage drive type power semiconductor switching device capable of speeding up di/dt and dv/dt even during large-current driving to thereby reduce the switching loss is disclosed. This power semiconductor switching device gate driving circuit includes a drive circuit which applies a drive signal to... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070200615 - Driver circuit: A driver circuit for powering an electronic device has a voltage source, two charge pump arrangements each having a diode connected in series with a capacitor. The charge pump arrangements are connected to the voltage source and the capacitors are charged, during a first phase, to a positive voltage level... Agent: Baker Botts, L.L.P.

20070200616 - Band-gap reference voltage generating circuit: A band-gap reference voltage generating apparatus is disclosed. The band-gap reference voltage generating apparatus according to the present invention includes an operational amplifier unit that is driven by a bias voltage and outputs an operational amplifying signal using a first voltage and a second voltage as input voltages; a voltage... Agent: Venable LLP

20070200617 - Architecture for reducing leakage component in semiconductor devices: An architecture for reducing leakage component in semiconductor devices using a gated power supply is based on the supply being split into two parts. An alternate inverter is connected to a different power rail derived from the same single power rail. The power rails are enabled and disabled according to... Agent: Allen, Dyer, Doppelt, Milbrath & Gilchrist P.A.

20070194811 - Method and arrangement for interference compensation in a voltage-controlled frequency generator: The invention, which relates to a method and an arrangement for interference compensation in a phase-locked loop comprising a voltage-controlled frequency generator, wherein the frequency generator is tuned to a nominal frequency by a tuning voltage Vtune and whose actual frequency is compared with a reference frequency by means of... Agent: Nxp, B.v. Nxp Intellectual Property Department

20070194812 - Line regulator with high bandwidth (bw) and high power supply rejection ratio (psrr) and wide range of output current: Aspects of a method and system for a linear regulator with high bandwidth, PSRR, and a wide range of output current are provided. A method for isolating voltages in a circuit may comprise applying a reference voltage to an isolation resistor based on a supply voltage. An internal voltage at... Agent: Mcandrews Held & Malloy, Ltd

20070194813 - Variable passive components with high resolution value selection and control: The present system provides a method for varying the value of passive components in electronic circuits. Passive components can range from basic resistors, capacitors, and inductors to complex, structures such as transmission lines and resonant cavities. Value selection and variation can either be dynamically performed during circuit operation or as... Agent: Thelen Reid Brown Raysman & Steiner, LLP

20070194814 - Current drive device: The current drive device of the present invention includes: a current source transistor for allowing a preset drive current to flow to a drain; a cascode transistor cascode-connected to the current source transistor; a switch circuit for switching ON/OFF flow of the drive current through the drain of the cascode... Agent: Mcdermott Will & Emery LLP

20070194815 - Enhanced delay matching buffer circuit: A buffer circuit includes an input stage including at least one MOS device having a first threshold voltage associated therewith, the input stage being adapted to receive an input signal referenced to a first voltage supply. The buffer circuit further includes an output stage including at least one MOS transistor... Agent: Ryan, Mason & Lewis, LLP

20070194816 - Switching arrangement for interconnecting electrolytic capacitors: Switching arrangement for interconnecting electrolytic capacitors that comprises an electronic switch formed by a semiconductor device and a delay member. The semiconductor device has a control input which is, through an RC-type delay member, connected to a control input (VS) supplying the switching signal. The switching arrangement has a predetermined... Agent: Fitch, Even, Tabin & Flannery

20070194817 - Spread-spectrum clocking: A state machine circuit may be used to control a multiplexing circuit that selects and provides respective ones of multiple input clock signals to a clock-synthesizing circuit that generates a synthesized clock signal in response to such input clock signals. The state machine circuit may, for example, be configured so... Agent: Wolf Greenfield & Sacks, P.C.

20070194818 - Phase locked loop circuit having set initial locking level and control method thereof: A phase locked loop circuit and a control method thereof. A phase locked loop circuit includes a phase detecting and correcting block configured to detect a phase difference between a reference clock and a feedback clock, and to correct the phase of the feedback clock such that the phase of... Agent: Venable LLP

20070194819 - Method for synchronizing a clock signal with a reference signal, and phase locked loop: A method for synchronizing a clock signal with a reference signal is disclosed. One embodiment has a first synchronization part which has a bit pattern having a particular clock period, a pause whose length is a multiple of this clock period plus a fraction of the clock period, and a... Agent: Dicke, Billig & Czaja

20070194825 - Adaptive delay-locked loops and methods of generating clock signals using the same: A delay-locked loop (DLL) includes a delay line and a control circuit. The delay line delays an input clock signal based on at least one phase control signal to generate an output clock signal. The at least one phase control signal indicates whether the output clock signal leads or lags... Agent: Harness, Dickey & Pierce, P.L.C

20070194822 - Digital dll circuit: A digital DLL circuit includes: a register configured to hold a delay target value; an oscillator; a first counter configured to count an external reference clock or an oscillation output from the oscillator; a second counter configured to count the oscillation output from the oscillator or the external reference clock... Agent: Rader Fishman & Grauer PLLC

20070194823 - Digital dll circuit: A digital DLL circuit includes: a first register configured to hold a delay specifying value to specify a delay; a second register configured to specify a correction value for a gate delay inside an LSI; a digitally-controlled variable delay circuit; and a control circuit configured to produce a delay control... Agent: Rader Fishman & Grauer PLLC

20070194824 - Digital dll circuit: A digital DLL circuit includes: a first register configured to hold a first delay specifying value to specify a delay of a rising edge side of a signal; a second register configured to hold a second delay specifying value to specify a delay of a falling edge side of a... Agent: Rader Fishman & Grauer PLLC

20070194821 - Continuous high-frequency event filter: A circuit and method for generating an active output signal in response to detecting N events, which are represented by an event signal. A counter circuit is configured to increment and decrement through a sequence of values in response to the event signal. Detection logic coupled to the counter circuit... Agent: Kimton N. Eng, Esq. Dorsey & Whitney LLP

20070194820 - Phase delay detection apparatus and method with multi-cycle phase range of operation: A method and apparatus is provided to assure that a delay line control loop will only lock at a desired phase difference—e.g., 360 degrees (and not at the desired phase difference plus a multiple of 360 degrees), between its input and output signals. The phase delay detector of the invention... Agent: Law Office Of John Ligon

20070194826 - Circuit capable of self-correcting delay time and method thereof: The present invention discloses a circuit capable of self-correcting delay time that includes a clock generating unit for generating a clock signal, a processing unit for producing a counter enable signal according to a reference clock, and a counting unit for receiving the counter enable signal and using the clock... Agent: North America Intellectual Property Corporation

20070194827 - Device and method for pulse width modulation: A device and a method for pulse width modulation is disclosed, wherein the temporal occurrence of both the respectively rising and the respectively falling edges of a pulse signal is varied.... Agent: Dicke, Billig & Czaja

20070194828 - Method for generating a signal representative of the current delivered to a load by a power device and relative power device: An integrated power transistor includes emitter or source regions, and a comb-like patterned metal electrode structure interconnecting the emitter or source regions and defining at least one connection pad. The comb-like patterned metal electrode structure includes a plurality of fingers. A current sensing resistor produces a voltage drop representative of... Agent: Allen, Dyer, Doppelt, Milbrath & Gilchrist P.A.

20070194829 - Integrated circuit clock distribution: A circuit is provided with a plurality of interconnected logic blocks, a main clock generator for distributing a reference clock signal to the logic blocks. Each logic block in the circuit comprises a local clock generator that generates a set of synchronized local clock signals from the reference clock signal... Agent: Nxp, B.v. Nxp Intellectual Property Department

20070194830 - High performance level shift circuit with low input voltage: A level shift circuit adds two NMOS transistors or two PMOS transistors between the NMOS transistors and PMOS transistors at the VP-side and the VN-side and connects the gates of the added transistors to the two output terminals. By this architecture, the level shift circuit of the present invention can... Agent: Norman P. Soloway Hayes Soloway P.C.

20070194831 - Signal differentiation with differential conversion circuit: A circuit for transmitting signals includes a transformer having an input side and an output side, the input side having a first end and a second end. A first transistor is coupled to the first end of the transformer, the first transistor being configured to provide a first signal to... Agent: Townsend And Townsend And Crew, LLP

20070194832 - Method for reducing insertion loss and providing power down protection for mosfet switches: An FET switch comprising a single or parallel opposite polarity FETS is illustrated with wells that are driven from internal power rails. The internal power rails are logically coupled by other driving FET switches to, in one case, the higher of a positive power supply or signal level wherein the... Agent: Cesari And Mckenna, LLP

20070194833 - Memory cell structure of sram: Disclosed is an SRAM including a latch circuit, first and second write transfer gates, first and second write buffer transistors, read driver transistor, and read transfer gate. A write path is formed by connecting first and second write transfer gates and first and second write buffer transistors to the latch... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070194834 - Semiconductor integrated circuit: The high level of a drive input signal for driving a high-side switch for precharge and a low-side switch for driving output in response to a clock signal is set to the level of a boosted output voltage. The low level of the drive input signal is set to the... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20070194835 - Circuit and method for powering up an integrated circuit and an integrated circuit utilizing same: The present invention is a circuit and method for providing a reference voltage and/or one or more circuit/circuit-block enabling signals for an IC. As the voltage level on a power supply line ramps upward towards or above a nominal operating voltage, a first threshold voltage detector circuit segment may be... Agent: Eitan Law Group C/o LandonIPInc.

20070194836 - Precharged power-down biasing circuit: A power-down biasing circuit includes a current source connected to a drain of a first NMOS transistor through a first switch. A gate of the first NMOS transistor is connected to the current source, and a source of the first NMOS transistor is connected to ground. A first pre-chargeable capacitor... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

20070194838 - Current mirror with improved output impedance at low power supplies: A current mirror circuit arrangement is formed to maintain a high output impedance when utilized with a relatively low voltage power supply. A common mode voltage regulator circuit is utilized in conjunction with the output branch of the current mirror to eliminate the need for an additional active device in... Agent: Wendy W. Koba, Esq.

20070194837 - Oled panel and related current mirrors for driving the same: A current mirror for driving an OLED panel is provided. The current mirror of the present invention adopts low voltage MOS transistors as the primary part of the current mirror so as to provide currents with high uniformity. The present invention also utilizes high voltage devices to bias the current... Agent: North America Intellectual Property Corporation

20070194840 - Method and circuit for adjusting an rc element: A method for adjusting an RC element with a capacitive element with adjustable capacitance, in particular a capacitor, and/or a resistive element with adjustable resistance, in particular an ohmic resistance, is provided. Multiple adjustment cycles are performed, wherein each adjustment cycle sets a standard value for the capacitance of the... Agent: Mcgrath, Geissler, Olds & Richardson, PLLC

20070194839 - Tunable balanced loss compensation in an electronic filter: The invention provides a system for providing tunable balanced loss compensation in an electronic filter. Tunable balanced loss compensation is provided by using cross-connected balanced transconductors and self-connected balanced transconductors. The cross-connected balanced transconductors and the self-connected transconductors compensate the unbalanced loss across the electronic filter. The self-connected balanced transconductors... Agent: William L Botjer

20070194841 - Semiconductor integrated circuit device: A semiconductor integrated circuit device provided with a first circuit block BLK1, a second circuit block DRV1 and a conversion circuit MIO1 for connecting the first circuit block to the second circuit block. The first circuit block includes a first mode for applying a supply voltage and a second mode... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20070188198 - Device and system for controlling current to a load: A device and system for controlling current from plural parallel power sources having inrush current hot-swapping capabilities to a load are disclosed. The current controlling device includes a load line for delivering currents from the outputs of the power sources; a current sensor for measuring the load current; and a... Agent: Texas Instruments Incorporated

20070188200 - Input buffer for semiconductor memory apparatus: Disclosed are an input buffer, and more particularly, a technique that is capable of improving the operation speed of the input buffer by improving response speed with respect to an input signal. The input buffer includes a buffer unit that operates when an activation control signal is activated, compares the... Agent: Venable LLP

20070188199 - X-y stage driver having locking device and data storage system having the x-y stage driver: An X-Y stage driver having a locking device and a data storage system having the X-Y stage driver. The X-Y stage driver includes an X-Y stage; a supporting unit that supports the X-Y stage and has elastic beams that support corners of the X-Y stage; a driving unit that drives... Agent: Sughrue Mion, PLLC

20070188201 - Small swing signal receiver for low power consumption and semiconductor device including the same: A circuit including a voltage boost circuit coupled to a first node and a second node, and configured to apply a boosted first node voltage to the second node; and an inverter circuit coupled to the first node, the second node, and a third node, and configured to generate a... Agent: Marger Johnson & Mccollom, P.C.

20070188202 - Power control circuit: An exemplary power control circuit includes a voltage divider, a switching circuit, and a detecting circuit. The voltage divider receives power from a first power supply which is connected to a microprocessor. The switching circuit is connected between a second power supply and the microprocessor. The detecting circuit is connected... Agent: PCe Industry, Inc. Att. Cheng-ju Chiang Jeffrey T. Knapp

20070188204 - Retiming circuits for phase-locked loops: Circuits and methods for retiming a frequency-divided clock are provided. A first sampling circuit samples the frequency-divided clock with a rising edge of a sampling clock. A second sampling circuit samples the frequency-divided clock with a falling edge of the sampling clock. A multiplexer in communication with the first and... Agent: Fish & NeaveIPGroup Ropes & Gray LLP

20070188203 - Semiconductor integrated circuit having built-in pll circuit: A semiconductor integrated circuit having a built-in PLL circuit which has two charge pump circuits for charging and discharging capacitive elements of a loop filter in response to signals generated by a phase comparator circuit. One of the two charge pump circuits has current sources which generate current values smaller... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20070188205 - Differential charge pump: A differential charge pump includes a differential charge pump unit, current adjusting device, and common mode voltage control circuit. The differential charge pump unit is used for generating a output voltage signal according to a pump-up signal and a pump-down signal. The current adjusting device is coupled to the differential... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070188206 - Delay locked loop with a function for implementing locking operation periodically during power down mode and locking operation method of the same: A Delay Locked Loop (DLL) having a function of periodically executing a locking operation during a power down mode and a locking operation method of the same, which includes a global clock generator, a clock delay unit, and a power down control unit. The power down control unit, in response... Agent: Mayer, Brown, Rowe & Maw LLP

20070188207 - Output driver with slew rate control: A circuit and method for controlling a slew rate of an output buffer. A pre-driver is provided that drives an input of an output pad driver of the output buffer. An output slew rate of the pre-driver is electronically selected among at least two electronically selectable slew rates. An output... Agent: Patterson, Thuente, Skaar & Christensen, P.A.

20070188208 - Semiconductor integrated circuit: In a semiconductor integrated circuit including first and second circuits whose inputs/outputs are in cross-connection, an output node of the first circuit is driven on the basis of a first input signal, and an output node of the second circuit is driven on the basis of a second input signal.... Agent: Stanley P. Fisher Reed Smith Hazel & Thomas LLP

20070188209 - Phase adjuster circuit and phase adjusting method: A phase adjustor circuit and a phase adjusting method are capable of preventing a phase shift amount from fluctuating even in the case where a frequency of a transmission carrier wave of a sensor signal fluctuates. A chopping wave converter circuit converts a pulse string signal into a chopping wave.... Agent: Arent Fox PLLC

20070188210 - Timing controller and controlled delay circuit for controlling timing or delay time of a signal by changing phase thereof: A controlled delay circuit has a first gate chain, and a second gate chain. The first gate chain is used to measure a time difference between a changeover point of a first control signal and a changeover point of a second control signal. The second gate chain, which receives third... Agent: Armstrong, Kratz, Quintos, Hanson & Brooks, LLP

20070188211 - Level-converting flip-flop and pulse generator for clustered voltage scaling: Provided is a level converting flip-flop for clustered voltage scaling and a level-converting pulse generator for use in the flip-flop. The flip-flop may include a pulse generator that receives an input clock signal with a high level equal to a first level and generates a pulse signal with a high... Agent: Harness, Dickey & Pierce, P.L.C

20070188212 - Semiconductor integrated circuit device: A disclosed semiconductor integrated circuit device includes a selection circuit that is supplied with a first clock signal and a second clock signal, a selection signal, and a switching signal, and configured to select one of the first clock signal and the second clock signal according to the selection signal... Agent: Ladas & Parry LLP

20070188213 - Method and apparatus for robust mode selection with low power consumption: A low power method and apparatus for selecting operational modes of a circuit. One circuit according to the teachings of the disclosed method and apparatus includes a first current limiting circuit coupled between a selector terminal and a first voltage bus. The first current limiting circuit is adapted to vary... Agent: Blakely Sokoloff Taylor & Zafman

20070188214 - Semiconductor device: A rectifier circuit configured with a conventional configuration using an operational amplifier and a diode by a thin film transistor over an insulating substrate cannot exhibit the performance of a rectifier circuit due to the low stability of operational amplifier and the low high-frequency characteristic. Therefore, the rectifier circuit requires... Agent: Eric Robinson

20070188215 - A-ab transconductor: A transconductor including circuitry for automatically selecting a non-linear class A operation or a linear class AB operation based on an input signal to be processed to generate an output signal, and for automatically adjusting current from a power supply to a level needed for operation of the transconductor.... Agent: Stmicroelectronics Inc. C/o Wolf, Greenfield & Sacks, P.C.

20070188216 - Constant current circuit: A constant current circuit includes first and second depression type MOS transistors having drains connected to a high electric potential side; and first, second, and third enhanced type MOS transistors having sources connected to a low electric potential side.... Agent: Dickstein Shapiro LLP

20070188217 - Signal output circuit and semiconductor integrated circuit: A signal output circuit is disclosed that supplies a signal from a first circuit that is driven based on a first reference voltage to a second circuit that is driven based on a second reference voltage. The signal output circuit includes a first control circuit that draws a current to... Agent: Ladas & Parry

20070188218 - Peak power suppressor and peak power suppressing method: A peak power suppressor for facilitating realization of a desired peak factor without increasing the device scale and without degrading the use efficiency of the storage area. A clipping section (102) suppresses the peak power of the transmission signal according to the clipping coefficient (a). A filter section (103) limits... Agent: Stevens, Davis, Miller & Mosher, LLP

20070182458 - Sense amplifier flip flop: A sense amplifier flip flop comprises a pre-charging portion connected between a first power voltage and first and second nodes and pre-charging the first and second nodes to a predetermined voltage in response to a clock signal, a differential input portion connected between a second power voltage and third and... Agent: Marger Johnson & Mccollom, P.C.

20070182457 - Transparent conductor and panel switch: The present invention provides a transparent conductor comprising a successive lamination of a support, a conductive particle layer containing a conductive particle and a first binder, and a conductive film layer containing a bead and a second binder; wherein a surface of the conductive film layer opposite from the conductive... Agent: Oliff & Berridge, PLC

20070182459 - Transistor arrangement for rectifier and inverter: The invention relates to a transistor arrangement (1) comprising a transistor (10), which is provided with first and second connections (12, 14) and a control connection (16) for controlling a current flow (iD) between said first and second connections (12, 14), a signal processing device (22) exposed to the transistor... Agent: Michael J. Striker

20070182460 - Dual output differential line driver using single current: Box switches are stacked sharing a common current from power sources. The power sources may be current, voltage or a combination of such sources. In preferred embodiments, the transistor switches in the box switches may be paralleled by different polarity transistors that will act to better balance and make symmetrical... Agent: Cesari And Mckenna, LLP

20070182462 - Output driver capable of controlling a short circuit current: An output driver capable of controlling a short circuit current includes a driving unit and a driving control unit. The driving unit receives a first driving signal and a second driving signal in response to a control signal and generates an output signal. The driving unit control unit includes a... Agent: Frank Chau, Esq. F. Chau & Associates, LLC

20070182461 - Resonant line drivers: An electronic driver circuit for comnmunicating a logic value along a conductor (12) from one part of a system (10) to another (14) by representing each of two logic values by one of two logic levels (VDD, Vss).A capacitor (CR1) reduces ground and power reference differences between a chip containing... Agent: Townsend And Townsend And Crew, LLP

20070182463 - Area efficient programmable frequency divider: A programmable high-speed frequency divider is provided in which a stage for forming a frequency divider, which is capable of being programmed with a programmable dividing ratio, is simplified in order to reduce the area and circuit complexity. The programmable frequency divider includes a first synchronizing element coupled to an... Agent: Fleit, Kain, Gibbons, Gutman, Bongini & Bianco P.l.

20070182465 - Method and system for synchronizing phase of triangular signal: A multiplicity of electronic devices is provided to generate triangular wave signals variable between an upper and lower limit voltages by charging or discharging capacitors. One of the triangular wave signals serves as a master triangular wave signal for controlling the phases of the remaining (or slave) triangular wave signals.... Agent: Hogan & Hartson L.L.P.

20070182464 - Triangular wave generation circuit: An accurate intermittent triangular wave signal without waveform distortion is generated by a triangular wave generation circuit 1 including a rectangular wave generation circuit 111 for generating an intermittent rectangular wave signal in which a rectangular wave interval and a direct current interval of a predetermined level are repeated; an... Agent: Oliff & Berridge, PLC

20070182466 - Reset detector: A reset detector is disclosed, which monitors the hardware reset of the subsystem(s) involved, in order to verify that the hardware reset has placed the subsystem in a correct reset state. Thus, in order to verify that an initial hardware reset has occurred, the subsystem software (e.g., during boot-up) detects... Agent: Honeywell International Inc.

20070182467 - Dpll circuit having holdover function: The invention relates to a digital synchronization network, and provides a DPLL circuit having a holdover function that generates a high-precision reference clock with a temperature correction to perform a free-running frequency control at a holdover time. In a holdover mode of the DPLL circuit using a DDS, the DPLL... Agent: Armstrong, Kratz, Quintos, Hanson & Brooks, LLP

20070182471 - Dll circuit and method of controlling the same: A delayed lock loop (DLL) circuit includes: a phase conversion control unit configured to latch an initial value of a phase comparison signal, and output the latched signal as a phase conversion control signal. A phase converting unit configured to control the phase of a delay clock on the basis... Agent: Venable LLP

20070182468 - Clock signal synchronizing device, and clock signal synchronizing method: d

20070182470 - Device and method for the synchronization of clock signals and adjustment of the duty cycle of the clock signal: A device for synchronizing an input clock signal with an output clock signal is disclosed. One embodiment includes includes a bistable trigger circuit for controlling the edges of a clock signal fed to a first delay, a second phase comparator for determining the phase between the first clock signal delayed... Agent: Dicke, Billig & Czaja

20070182469 - Temperature compensation via power supply modification to produce a temperature-independent delay in an integrated circuit: A method and circuitry for adjusting the delay of a variable delay line (VDL) in a delay locked loop (DLL) or other delay element or subcircuit on an integrated circuit is disclosed. Such delay circuitry will inherently have a delay which is a function of temperature. In accordance with embodiments... Agent: Wong, Cabello, Lutsch, Rutherford & Brucculeri, L.L.P.

20070182472 - Duty correction circuit of digital type for optimal layout area and current consumption: The present invention relates to a duty correction circuit that corrects a distorted duty of a clock signal using a delay unit and a delay controller, thereby reducing the layout area and current consumption. The duty correction circuit includes a repeater that generates a clock signal having the same phase... Agent: Ladas & Parry LLP

20070182473 - Pulsed static flip-flop: A pulsed static flip-flop comprises a first logic device which combines a logic signal with a pulsed signal and outputs a set signal, a second logic device which logically combines the logic signal with a complementary pulsed signal and outputs a reset signal; and a latch device comprising storage means... Agent: Maginot, Moore & Beck Chase Tower

20070182474 - Set and segr resistant delay cell and delay line for power-on reset circuit applications: A delay line appropriate for use in a POR circuit or other integrated circuit in a space environment combines three separate circuit techniques to improve performance without unnecessarily increasing circuit area or adding to manufacturing costs when compared to a simple inverter delay line. The delay line of the present... Agent: Hogan & Hartson LLP

20070182475 - Semiconductor integrated circuit: This invention provides a technique for enhancing an operating frequency and improving reliability in a system using at least level sense type sequence circuits as a plurality of sequence circuits. A microcomputer includes a clock generator configured as a clock supply source, functional modules operated in sync with a clock... Agent: Miles & Stockbridge PC

20070182476 - Isi reduction technique: The invention refers to signal processing circuits, more particularly, to switch capacitor circuits, and methods for reducing inter-symbol-interference. A switch capacitor circuit with reduced Inter-Symbol-Interference effect is provided, comprising: a voltage source, a first capacitor, a second capacitor, and at least one switch configured to be switched in a way... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

20070182479 - Semiconductor memory device including circuit for blocking operation of bias circuit, and method of generating bias voltage: Provided are a semiconductor memory device comprising a blocking circuit that blocks the operation of a bias circuit, and a method of generating a bias voltage. In the semiconductor memory device, the bias circuit is disabled by using the blocking circuit in a self-refresh mode, and the output terminal of... Agent: Mills & Onello LLP

20070182478 - Voltage reference circuit and current reference circuit using vertical bipolar junction transistor implemented by deep n-well cmos process: A voltage reference circuit and a current reference circuit using a vertical bipolar junction transistor (BJT) implemented by a deep N-well complementary metal-oxide semiconductor (CMOS) process, wherein the voltage reference circuit generates a constant reference voltage regardless of temperature and includes an amplifier element having a positive input terminal and... Agent: Frank Chau, Esq. F. Chau & Associates, LLC.

20070182477 - Band gap reference circuit for low voltage and semiconductor device including the same: A band gap reference circuit and a semiconductor device including the band gap reference circuit. The band gap reference circuit comprises a comparator, a first current source circuit, a second current source circuit, a first load circuit, and a second load circuit. The comparator compares a first voltage and a... Agent: Mayer, Brown, Rowe & Maw LLP

20070182480 - Complex filter circuit: Disclosed is a complex elliptic filter having an order of three or higher which receives two differential signals that differ in phase from each other by 90 degrees are applied and outputs two differential signals that differ in phase from each other by 90 degrees. The complex filter circuit has... Agent: Mcginn Intellectual Property Law Group, PLLC

20070176646 - Cascode-type current mode comparator and receiver, and semiconductor device having the same: A current mode comparator for a semiconductor device is disclosed. The current mode comparator may include a logic circuit coupled to a voltage sensing node, a first cascode coupled to the voltage sensing node and a first power node, and a second cascode coupled to the voltage sensing node and... Agent: Harness, Dickey & Pierce, P.L.C

20070176645 - Active current cancellation for high performance video clamps: An apparatus comprising a first circuit, a second circuit and a third circuit. The first circuit may be configured to generate a video input signal having a voltage. The second circuit may have a finite input resistance configured to generate a current in response to presenting the voltage across the... Agent: Lsi Logic Corporation

20070176647 - Clock rate adjustment apparatus and method for adjusting clock rate: A clock rate adjustment apparatus and a method for adjusting a clock rate of a clock for an optical storage system are provided. The clock rate adjustment apparatus comprises an indication provider, a throughput rate detector, and a clock generator. The method performs the following steps. The indication provider generates... Agent: Patterson, Thuente, Skaar & Christensen, P.A.

20070176648 - Precisely adjusting a local clock: Accurate correction of a local clock that avoids excessive drift in the local clock while avoiding an accumulation of quantization errors. A local clock according to the present techniques generates a local time by accumulating a sequence of rate coefficients selected from a plurality of rate coefficients using a series... Agent: Agilent Technologies Inc.

20070176649 - Circuit for differential signals: A method and integrated circuit for the transmission of differential signals with a signal and a complementary signal is disclosed. For trimming the edge steepness of the signal with that of the complementary signal, the integrated circuit has a first driver for generating the signal, and a second driver for... Agent: Dicke, Billig & Czaja

20070176650 - High-speed, low-power input buffer for integrated circuit devices: A high-speed, low-power input buffer for an integrated circuit device in which the input voltage (VIN) is coupled to both a pull-up and a pull-down transistor. In accordance with a specific embodiment, the input buffer utilizes a reference voltage input (VREF) during a calibration phase of operation but not when... Agent: Hogan & Hartson LLP

20070176651 - Circuits for locally generating non-integral divided clocks with centralized state machines: Circuitry for locally generating a ratio clock on a chip. The circuitry includes circuitry for generating a global clock signal having a global clock cycle. A state machine includes a counter going through a complete cycle in response to a non-integer number of global clock cycles. The state machine generates... Agent: Cantor Colburn LLP-ibm Poughkeepsie

20070176652 - Method for locally generating non-integral divided clocks with centralized state machines: A method for locally generating a ratio clock on a chip includes generating a global clock signal having a global clock cycle. A centralized state machine is provided that includes a counter going through a complete cycle in response to a non-integer number of global clock cycles, the centralized state... Agent: Cantor Colburn LLP-ibm Poughkeepsie

20070176653 - Methods and systems for locally generating non-integral divided clocks with centralized state machines: A method for locally generating a ratio clock on a chip includes generating a global clock signal having a global clock cycle. A centralized state machine includes a counter going through a complete cycle in response to a non-integer number of global clock cycles, the state machine generating a control... Agent: Cantor Colburn LLP-ibm Poughkeepsie

20070176654 - Semiconductor memory device, power supply detector and semiconductor device: A semiconductor memory device comprises a n-channel type MOSFET in which a drain and a gate are connected to an external power supply and a source and a back gate are connected each other, a node connected to the source and the back gate of the n-channel type MOSFET, and... Agent: Oblon, Spivak, Mcclelland, Maier & Neustadt, P.C.

20070176655 - Differential charge pump with open loop common mode: A differential charge pump with common mode and active regulators is presented. Either type of regulator may be used to improve the performance characteristics of the differential charge pump. The active regulator increases the output range of the differential amplifier. The common mode regulator establishes the common mode voltage of... Agent: Honeywell International Inc.

20070176657 - Delay-locked loop circuit of a semiconductor device and method of controlling the same: A delay-locked loop (DLL) circuit includes a standby signal generating circuit, a front stage circuit, and a back stage circuit. The standby signal generating circuit generates a first standby signal and a second standby signal in response to an active signal, a crock enable signal, a first column address strobe... Agent: F. Chau & Associates, LLC

20070176656 - Delay-locked loop circuits: A delay-locked loop (DLL) circuit has a reference signal input for a receiving a periodic reference signal and a number of signal outputs for outputting respective output signals derived from the reference signal and having a desired phase relationship with one another. The DLL circuit comprises a voltage controlled delay... Agent: Dickstein Shapiro LLP

20070176658 - Timing adjustment circuit: Three flip-flops receive a common data signal input through a data terminal based on different timing signals which are obtained from an external timing signal and differ from one another by a specific delay step. A judging circuit judges whether or not the output data of the three flip-flops coincide... Agent: Young & Thompson

20070176660 - Systems and methods for pulse width modulating asymmetric signal levels: Systems and methods for pulse width modulating waveforms to represent asymmetric signal levels using pulses that are symmetric within their respective switching periods. One embodiment comprises a pulse width modulation system including an asymmetric correction unit and a pair of modulators. The asymmetric correction unit receives samples of an input... Agent: Law Offices Of Mark L. Berrier

20070176659 - Duty cycle error calculation circuit for a clock generator having a delay locked loop and duty cycle correction circuit: A system and method for generating a correction signal for correcting duty cycle error of a first clock signal relative to a second complementary clock signal. Changes to a time difference between high- and low-portions of the first clock signal are detected and the correction signal is generated in response... Agent: Kimton N. Eng, Esq. Dorsey & Whitney LLP

20070176661 - Data delay control circuit and method: A data delay control circuit and method that can adaptively reflect changes in an operating environment, such as an operating temperature, an operating voltage and a manufacturing process of a semiconductor chip. The data delay control circuit is designed to be able to adaptibly delay data when an expected delay... Agent: Frank Chau, Esq. F. Chau & Associates, LLC

20070176662 - Dual-edge shaping latch/synchronizer for re-aligning edges: Integrated circuit and process for aligning a first signal with a second signal. The integrated circuit includes a single latch, a switch control circuit coupled to an input of the single latch to align an edge of the first signal with an edge of the second signal, and a second... Agent: Greenblum & Bernstein, P.L.C

20070176663 - Offset signal phasing for a multiple frequency source system: A tunable multiple frequency source system employing offset signal phasing includes a first frequency source, a phase delay element, and a second frequency source configured to operate concurrently with the first frequency source. The first frequency source includes an input coupled to receive a reference input signal and an output... Agent: Clifford B. Perry

20070176664 - Programmable gain attenuator for track and hold amplifiers: A programmable gain attenuator (PGA) in particular to be used in a track-and-hold circuit is disclosed. The PGA is located in the feedback path around an operational amplifier. One tap switch is used to connect one PGA section to the output of the operational amplifier. The PGA section is capable... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

20070176665 - Variable voltage attenuator circuits: Methods and circuits are provided for controlling a signal applied to a control terminal of a variable voltage attenuator. In one embodiment, a method comprises detecting an output signal of the variable voltage attenuator, generating a logarithm of the detected output signal of the variable voltage attenuator, and generating the... Agent: Wolf Greenfield & Sacks, P.C.

20070176668 - Level shifter circuit: A level shifter circuit, which includes a Schmitt trigger function, shifts voltage of a high level signal into a low voltage and shifts a signal at an intermediate value of an input voltage. The level shifter circuit includes an input terminal connected to low and high voltage circuits. The low... Agent: Freescale Semiconductor, Inc. Law Department

20070176666 - Level translator for adapting a signal to a voltage level: A level translator for translating a digital signal from a first voltage level to another voltage level having a higher voltage assigned to the high state of the signal comprises a latch and a pair of N-MOS transistors being coupled to the latch. This design is improved in that the... Agent: Sterne, Kessler, Goldstein & Fox P.l.l.c.

20070176667 - Voltage supply interface circuit: A monolithic interface circuit for providing a voltage, from a control circuit supplied by a supply voltage referenced to a reference voltage, to a terminal likely to be at a high voltage with respect to the reference voltage, comprising a high-voltage N-channel MOS transistor having its gate intended to receive... Agent: Stmicroelectronics Inc. C/o Wolf, Greenfield & Sacks, P.C.

20070176669 - Temperature compensation device and method thereof: A device and method for temperature compensation of an electronic device are disclosed. The device includes a temperature bias controller with a temperature sensor. A bias signal based upon a signal from the temperature sensor is provided to a first gate of a multiple fin gate field effect transistor (multigate... Agent: Larson Newman Abel Polansky & White, LLP

20070176671 - Charge pump circuit and electric appliance therewith: In a charge pump circuit, the through rate at which a clock signal is fed to charge transfer transistors is changed according to the output voltage. This configuration helps alleviate rush currents at start-up without unduly lowering efficiency.... Agent: Fish & Richardson P.C.

20070176670 - Charge pump based subsystem for secure smart-card design: A smart card includes a power source, a processing chip, and a charge-pump subsystem for powering the processing chip. The charge-pump subsystem includes a capacitor which is connected cyclically to the power source to charge the capacitor, to the processing chip to power the processing chip, and to ground to... Agent: Blank Rome LLP

20070176672 - Device and method for voltage regulator with stable and fast response and low standby current: An apparatus and method for regulating voltage levels. The apparatus includes a first transistor and a second transistor. The first transistor and the second transistor are each coupled to a first current source and a second current source. Additionally, the apparatus includes a third transistor coupled to the second transistor... Agent: Townsend And Townsend And Crew, LLP

20070176673 - Semiconductor integrated circuit apparatus and electronic apparatus: A semiconductor integrated circuit apparatus and an electronic apparatus having a power control function configured from power control MOS transistors in such a manner that leakage current and on resistance at the time of cut-off is sufficiently small in actual use. Semiconductor integrated circuit apparatus is comprised of a CMOS... Agent: Greenblum & Bernstein, P.L.C

20070176674 - Semiconductor integrated circuit: A coupling capacitor for converting the DC level between circuits is incorporated into a semiconductor integrated circuit to reduce the number components. A high-pass filter (34) having a cutoff frequency fC is composed of a coupling capacitor C1 that cuts off direct current between circuits (22) and (24), and a... Agent: Oliff & Berridge, PLC