Miscellaneous active electrical nonlinear devices, circuits, and systems inventions 03/07

20070069766 - Phase measurement device, method, program, and recording medium: When a signal having two or more frequency components is fed to a circuit to be measured, a phase of the signal output from the circuit to be measured is measured. A phase measurement device measures an output when an input signal having two input frequency components ω10 and ω20... Agent: Greenblum & Bernstein, P.L.C

20070069767 - Differential amplifier: A differential amplifier includes an amplification unit and a feedback unit. The amplification unit amplifies a voltage difference between a first input signal and a second input signal and outputs a first output signal and a second output signal. The feedback unit amplifies a voltage difference between a first feedback... Agent: Mcdermott Will & Emery LLP

20070069768 - Signal detection circuit capable of automatically adjusting threshold value: The signal detection circuit of the present invention includes: a comparison section for comparing the absolute value of a voltage of an input differential signal with a threshold voltage corresponding to a first detection level adjustment signal to detect presence/absence of an input signal and outputting a detection signal indicating... Agent: Mcdermott Will & Emery LLP

20070069769 - Transmission circuit for use in input/output interface: A transmission circuit includes a first-stage circuit, a second-stage circuit, a negative active feedback circuit and a current buffer. The first-stage circuit includes at least an active MOS device for receiving an input voltage and issuing a first voltage signal. The active MOS device has an inductive feature during operation... Agent: Bacon & Thomas, PLLC

20070069770 - High voltage tolerant input buffer operable in under-drive conditions: An input buffer includes a signal passing module for generating a first output signal in response to the input signal based on a comparison between the input signal and a first supply voltage thereof; a regulating module having a first input terminal receiving the input signal and a second input... Agent: L. Howard Chen, Esq. Kirkpatrick & Lockhart Preston Gates Ellis LLP

20070069771 - Mosfet transistor amplifier with controlled output current: A switched current source has a first voltage source, a second voltage source, and a third voltage source. A first transistor has a drain terminal coupled to one terminal of a load and a source terminal coupled to the third voltage source. A second transistor has drain, gate and source... Agent: Weiss & Moy PC

20070069780 - Delay cell of voltage controlled delay line using digital and analog control scheme: Provided is an analog/digital control delay locked loop (DLL). The DLL includes a phase detector for detecting a phase difference between an input clock signal and a feedback signal to provide an up detection signal or a down detection signal, a charge pump for generating an adjusted output current based... Agent: Blakely Sokoloff Taylor & Zafman

20070069781 - Delay locked loop: A delayed locked loop, capable of a duty cycle compensation, resets if a phase difference between outputs from delay blocks in the delay locked loop is over a predetermined amount after a delay locking state is achieved. The delay locked loop includes a duty cycle compensator for receiving first and... Agent: Mcdermott Will & Emery LLP

20070069772 - Delay locked loop circuit: A DLL circuit and a synchronous memory device perform stable operation in a power down mode although the entry and exit into/from the power down mode is repeated rapidly. The synchronous memory device operates in a normal mode and a power down mode. A delay locked loop (DLL) generates a... Agent: Mcdermott Will & Emery LLP

20070069773 - Delay locked loop circuit: A synchronous memory device having a normal mode and a power down mode includes a power down mode controller for generating a power down mode control signal in response to a clock enable signal, thereby determining onset or termination of a power down mode. A clock buffering unit buffers an... Agent: Mcdermott Will & Emery LLP

20070069775 - Delay locked loop circuit: A delay locked loop (DLL) circuit for a synchronous dynamic random access memory (SDRAM) enables a more stable operation when the semiconductor operates in a power-down mode for low power. The present invention can prevent a phase update operation from being interrupted when the DLL circuit enters a power-down mode.... Agent: Mcdermott Will & Emery LLP

20070069776 - Delay locked loop circuit: A delay locked loop (DLL) circuit for a synchronous dynamic random access memory (SDRAM) is provided. If a locking state is broken due to an external change such as a change of tCK or power supply voltage, indicating that a delay of a delay replication modeling unit involved in a... Agent: Mcdermott Will & Emery LLP

20070069778 - Delay locked loop circuit: A DLL of a memory device having a normal mode and a power down mode includes a clock buffer for buffering an external clock signal to output an internal clock signal. A power down mode controller generates a power down mode control signal to define the normal mode or the... Agent: Mcdermott Will & Emery LLP

20070069779 - Delay locked loop circuit: A delay locked loop increases an operation margin of a delay locked loop by using an output clock having more advanced phase than a DLL output clock. A clock delay compensation block receives an external clock signal to thereby generate a first multi clock and a second multi clock. A... Agent: Mcdermott Will & Emery LLP

20070069782 - Delay locked loop for high speed semiconductor memory device: A delayed locked loop supports increased operation frequency in a semiconductor memory device. An output driver for use in a delay locked loop includes a first driving block for receiving an output from the delay locked loop to generate a first DLL clock for outputting read data corresponding to a... Agent: Mcdermott Will & Emery LLP

20070069783 - Delay locked loop in synchronous semiconductor memory device and driving method thereof: A semiconductor memory device including a delay locked loop can minimize current consumption during a precharge power down mode. The delay locked loop includes a buffer control block for generating a clock buffer enable signal in response to first and second signals, wherein the first signal represents a precharge power... Agent: Mcdermott Will & Emery LLP

20070069777 - Dll driver control circuit: A Delay Locked Loop (DLL) driver control circuit is capable of reducing an amount of current consumption by preventing the output of unnecessary clocks. The DLL driver control circuit includes a DLL driver for driving a DLL clock and a DLL driver controller for generating a control signal to control... Agent: Mcdermott Will & Emery LLP

20070069774 - Semiconductor memory device having delay locked loop: A semiconductor memory device has a delay locked loop (DLL) with low power consumption. The semiconductor memory device includes a DLL for receiving an external clock to generate a DLL clock, an idle detector for detecting an idle state in which a command for driving a device is not supplied,... Agent: Mcdermott Will & Emery LLP

20070069784 - Open-loop slew-rate controlled output driver: A slew-rate controlled output driver for use in a semiconductor device includes a PVT variation detection unit having a delay line for receiving a reference clock in order to detect a delay amount variation of the delay line determined according to process, voltage and temperature (PVT) variation; a selection signal... Agent: Blakely Sokoloff Taylor & Zafman

20070069785 - Reduced voltage pre-charge multiplexer: An electronic device selects one of a plurality of input signals for coupling to an output channel. Individual pulldowns provide a separate pathway for each input, and are coupled to a common node which: is pre-charged to a voltage less than a system voltage. Each pulldown is coupled to a... Agent: Schneck & Schneck

20070069786 - Semiconductor memory device and driving method thereof: Provided is a semiconductor memory device and a driving method for initializing an internal logic circuit within the semiconductor memory device under a stable state of a source voltage without an extra reset pin. The semiconductor memory device includes a power-up signal generating unit for generating a power-up signal; an... Agent: Blakely Sokoloff Taylor & Zafman

20070069789 - Flip-flop circuit: A flip-flop circuit includes a first inverter for inverting a signal of a first node and transferring an inverted signal to a second node, and a second inverter for feeding back a signal of the second node and transferring a feedback signal to the first node. The second inverter includes:... Agent: Blakely Sokoloff Taylor & Zafman

20070069787 - Logic circuit: A first current source generating a current I0+I when a control signal is in ‘H’ level and a current I0 when it is in ‘L’ level, a current mirror circuit transferring a current generated in the first current source and composed of first and second MOS transistors, and a second... Agent: Mattingly, Stanger, Malur & Brundidge, P.C.

20070069788 - Output circuit of a semiconductor memory device and method of outputting data in a semiconductor memory device: An output circuit of a semiconductor memory device includes a first data path, a second data path and a third data path. The first data path transfers a sense output signal, and latches the sense output signal to output the sense output signal to a first node. The second data... Agent: Mills & Onello LLP

20070069790 - Skew tolerant phase shift driver with controlled reset pulse width: A phase shift driver for phase shifting an input clock signal at a first phase to generate an output signal at a second phase without missing subsequent input signals. Input logic circuitry of the phase shift driver may receive an input signal at a first phase. Output logic circuitry of... Agent: Meyertons, Hood, Kivlin, Kowert & Goetzel, P.C.

20070069791 - Adjustable delay cells and delay lines including the same: Delay lines include an adjustable delay cell that adjusts a speed at which an input signal to the adjustable delay cell is transmitted through the adjustable delay cell responsive to a control signal. A plurality of set delay cells are coupled in series with the adjustable delay cell that delay... Agent: Myers Bigel Sibley & Sajovec

20070069792 - Delay circuit: A delay circuit controls a delay time according to variation of a power supply voltage. In the delay circuit, the capacitance of a capacitor connected in parallel to the delay line is changed according to the change of the power supply voltage. Alternatively, a current is made to flow through... Agent: Mcdermott Will & Emery LLP

20070069793 - Method and system for high frequency clock signal gating: A differential clock signal gating method and system is provided, wherein a clock buffer circuit control path develops a clock gating signal with a timing relationship to a clock signal. The clock gating signal gates a buffer on the clock buffer circuit controlled path in communication with the clock signal... Agent: Driggs, Hogg & Fry Co. L.p.a.

20070069795 - Pulse control device: A pulse control device is maintained with a constant pulse width corresponding to a change of process or temperature. The pulse control device comprises a fuse set for selectively outputting a delay increase signal and a delay decrease signal that have a different state based on a cutting or non-cutting... Agent: Mcdermott Will & Emery LLP

20070069794 - System and method for generating self-aligned clock signals for consecutive circuit operations: A system and method of generating a clock signal are provided for driving a plurality of consecutive circuit phase operations. The method includes generating a clock signal, transmitting the clock signal to one circuit phase operation, and transmitting another clock signal to a previous circuit phase operation. A circuit configured... Agent: Stevens Law Group

20070069796 - Low-voltage down converter: A low-voltage level converter provides level conversion for multiple-supply voltages for very large scale integration (VLSI) systems. Low voltage-level down conversion is achieved at very low voltage operation for on-chip test circuitry for multiple-supply voltage systems. The converter includes an output driver PMOS FET (positive metal-oxide semiconductor field effect transistor)... Agent: Qualcomm Incorporated

20070069797 - Back gate biasing overshoot and undershoot protection circuitry: The signal switch has flat resistance across the input/output voltage range when in the ON state while still isolating input/output nodes from overshoots and undershoots when in the off state. The signal switch includes: a p channel switch coupled between a first input/output node and a second input/output node; an... Agent: Texas Instruments Incorporated

20070069798 - Switch circuit for high-frequency-signal switching: A switch circuit includes first and second input/output terminals; first depletion-mode transistors serially-connected between first and second nodes; second depletion-mode transistors serially-connected between third and fourth nodes; a common terminal connected to a connection node; a bias circuit feeding a first bias voltage to gates of the first depletion-mode transistors,... Agent: Young & Thompson

20070069799 - Internal voltage generator for preventing voltage drop of internal voltage: An internal voltage generating circuit is utilized to perform a TDBI (Test During Burn-in) operation for a semiconductor device. The internal voltage generator produces an internal voltage at a high voltage level, as an internal voltage, in not only a standby section but also in an active section in response... Agent: Mcdermott Will & Emery LLP

20070069803 - Charge-pump circuit: A circuit includes a plurality of stages each including a MOS transistor and a capacitor of which one end is connected to one of a drain and a source of the MOS transistor. The plurality of stages are connected with each other by cascade connection of the MOS transistors. A... Agent: Mcdermott Will & Emery LLP

20070069801 - Charge-pump type, voltage-boosting device with reduced ripple, in particular for non-volatile flash memories: Voltage-boosting device having a supply input receiving a supply voltage, and a high-voltage output. The device is formed by a plurality of charge-pump stages series-connected between the supply input and the high-voltage output. Each charge-pump stage has a respective enabling input receiving an enabling signal. A control circuit formed by... Agent: Seed Intellectual Property Law Group PLLC

20070069804 - High voltage generator and word line driving high voltage generator of memory device: A high voltage generator includes: a detection unit for comparing a reference voltage with a high voltage and detecting a voltage level of the high voltage; an oscillator selection unit for generating a first control signal and a second control signal in response to an output signal of the detection... Agent: Mcdermott Will & Emery LLP

20070069805 - Internal voltage generating circuit: An internal voltage generating circuit detects a level of a back bias voltage or a pumping voltage and controls a period of an oscillating signal based on the result of counting timing when the detected voltage is lower than a reference voltage. The internal voltage generating circuit includes a back... Agent: Mcdermott Will & Emery LLP

20070069802 - Internal voltage generator: An internal voltage generator supplies a stable internal voltage without increasing standby current. The internal voltage generator includes an internal voltage driver for supplying an internal voltage based on a control signal, a feedback circuit for supplying a feedback voltage having a voltage level proportional to the internal voltage, a... Agent: Mcdermott Will & Emery LLP

20070069800 - Negative charge-pump with circuit to eliminate parasitic diode turn-on: A negative charge-pump circuit for flash memory includes a well, a pass-gate transistor, a well bias circuit and a negative voltage recovery circuit. The pass-gate transistor has a source, a drain and a gate. The well bias circuit controls the well to remain one of zero biased and reverse biased.... Agent: Akin Gump Strauss Hauer & Feld L.L.P.

20070069806 - Operational amplifier and band gap reference voltage generation circuit including the same: A band gap reference voltage generation circuit includes a reference voltage output node; a current distributing block coupled between the reference voltage output node and a ground voltage terminal, distributing current and supplying a first voltage and a second voltage; an operation amplifying block comparing the first voltage with the... Agent: Blakely Sokoloff Taylor & Zafman

20070069808 - Internal voltage generator: An internal voltage generator includes a pull-up driver to pull-up drive a supply terminal of an internal voltage, a pull-down driver to pull-down drive the supply terminal of the internal voltage, a pull-up driving control means to turn on the pull-up driver when a first feedback voltage corresponding to the... Agent: Mcdermott Will & Emery LLP

20070069809 - Internal voltage generator: An internal voltage generator includes a voltage comparator operating in response to an enable signal, comparing a reference voltage with a feedback voltage and outputting a comparison signal through a first node. A driving controller outputs a drive control signal in response to the comparison signal. An output driver outputs... Agent: Mcdermott Will & Emery LLP

20070069807 - Voltage regulation having varying reference during operation: For one disclosed embodiment, a reference voltage signal is generated. Error in an output voltage signal at an output node is sensed based on the reference voltage signal. The output voltage signal is controlled based on the sensed error. The reference voltage signal is varied as the output voltage signal... Agent: Intel/blakely

20070069810 - Set/reset latch circuit, schmitt trigger circuit, and mobile based d-type flip flop circuit and frequency divider circuit thereof: A SET/RESET latch circuit, characterized by including a transistor 1 and 2 in which each emitter of said transistors is commonly connected to a current source, and a negative differential resistance diode 1 and 2 which are respectively connected to each collector of said transistor 1 and 2; and additionally... Agent: Greenblum & Bernstein, P.L.C

20070063741 - Testing of integrated circuit receivers: A method for testing a data recovery circuit (DRC) includes disturbing a running variable in a closed control loop of the DRC, as the DRC is processing a received test signal. Data recovered by the DRC, while the DRC was affected by the disturbance, is evaluated. Other embodiments are also... Agent: Blakely Sokoloff Taylor & Zafman

20070063742 - Secure and fast calculating unit: The calculating unit includes a dual rail input stage, a switching stage for a bit to be calculated and an output stage for an output bit, wherein the output stage provides a dual rail output. The switching stage is not implemented in dual rail technology but according to a “one-hot”... Agent: Darby & Darby P.C.

20070063743 - Video signal detection circuit: A signal detector for detecting and indicating the duration of a signal pulse by comparing the relative polarities of two voltages generated during the two states of the pulsed signal.... Agent: National Semiconductor Corporation C/o Vedder Price Kaufman & Kammholz

20070063744 - Clock switching circuit: This invention provides a clock switching circuit that can switch clocks without causing a hazard or a distortion of a duty ratio of the clocks. The clock switching circuit of this invention includes a first synchronization circuit that synchronizes a clock selection signal with a first clock, a second synchronization... Agent: Morrison & Foerster LLP

20070063745 - Support for conditional operations in time-stationary processors: In case of time-stationary encoding, every instruction that is part of the processor's instruction-set controls a complete set of operations that have to be executed in a single machine cycle. These operations may be processing several different data items traversing the data pipeline. Time-stationary encoding is often used in application-specific... Agent: Philips Intellectual Property & Standards

20070063746 - Active load arrangement: An active load arrangement is used to provide proper output load to an object TO under test. The arrangement Z comprises a voltage_controlled transistor MOSFET having a source S, a gate G and a drain D. The drain D is associated with the gate G and connected to an arrangement... Agent: Ericsson Inc.

20070063747 - Switching circuit having two mos-fets: A switching circuit of the present invention can be advantageously used in an electronic control unit mounted on an automotive vehicle. The switching circuit is constituted by a pair of P-channel MOS-FETs connected in series between an input terminal and an output terminal. Sources of both MOS-FETs are connected to... Agent: Posz Law Group, PLC

20070063748 - Delay locked loop structure providing first and second locked clock signals: A delay locked loop including a first circuit and a second circuit. The first circuit is configured to receive a clock signal having a frequency and to lock onto the clock signal and provide a first locked clock signal over a first frequency range and a second locked clock signal... Agent: Dicke, Billig & Czaja, P.l.l.c.

20070063749 - Matched current delay cell and delay locked loop: Matched current delay cells and a delay locked loop based on such cells that may be used for timing data interfaces between semiconductor devices is described. In one embodiment, the delay cell includes a delay cell having a PMOS portion and a NMOS portion, gates of the PMOS portion being... Agent: Blakely Sokoloff Taylor & Zafman

20070063750 - Timing vernier using a delay locked loop: A method for synchronizing a plurality of programmable timing verniers with a reference pulse signal, each of the verniers being programmable to one of a plurality of timing steps within a delay range determined by a control signal applied to a bias input. A first and second control vernier is... Agent: Borden Ladner Gervais LLP

20070063751 - Clock distribution circuit: A clock distribution circuit for suitably generating, transmitting, and receiving clock signals used in circuits that are configured with the same circuit topology is provided. The clock distribution circuit has a transmission buffer circuit that transmits a clock signal and an amplitude amplification buffer circuit that amplifies the amplitude of... Agent: Arent Fox PLLC

20070063752 - Master-slave flip flop: Master-slave flip flop including a master latch having a data input for receiving a data input signal, an inverting clock input for receiving a first clock signal, and a data output, a slave latch having a data input which is connected to the data output of the master latch, a... Agent: Dickstein Shapiro LLP

20070063754 - Frequency generator: A frequency generator is specified which includes a pulse generator with a downstream signal conditioning circuit. The pulse generator is designed for recurring emission of pulses. The signal conditioning circuit derives a signal at a desired frequency from higher harmonic frequency components of the electrical pulses. The circuit makes it... Agent: Eschweiler & Associates, LLC National City Bank Building

20070063753 - Waveform detection, in particular for the representation of the root mean square of a waveform: The instantaneous value of an intermediate waveform I is the instantaneous value of a unipolar waveform U multiplied through amplification by an upscaling factor UF of 1.5. A plateau value P is subtracted from the intermediate value I, and the result of this subtraction is multiplied by a multiplication factor... Agent: Stroock & Stroock & Lavan LLP

20070063755 - Method and apparatus for generating spread spectrum clock signals having harmonic emission suppressions: A method for generating spread spectrum clock signals having harmonic emission suppressions is disclosed. A set of delayed clock signals is initially generated by delaying a high-speed clock signal via a set of delay modules. Then, the leading edge of a first one of the delayed clock signals is selectively... Agent: Ibm Corporation RochesterIPLaw Dept. 917

20070063756 - Methods and apparatus for managing clock skew: An apparatus is disclosed which includes a signal generator providing a first signal having a first frequency; a clock tree operative to propagate the first signal to at least one clock mesh of the apparatus; and a final buffer operative to receive the first signal, provide a second signal having... Agent: Kaplan Gilman Gibson & Dernier L.L.P.

20070063757 - Method and system for dc offset correction loop for a mobile digital cellular television environment: Methods and systems for a DC offset correction loop for a mobile digital cellular television environment are disclosed. Aspects of one method may include removing at least a portion of a DC offset from output of an amplifier. The DC offset may be removed from a single stage amplifier, or... Agent: Mcandrews Held & Malloy, Ltd

20070063759 - Level shift circuit, display apparatus, and portable terminal: A level shift circuit formed on an insulating substrate, such as a glass substrate, using transistors with large characteristic variations, for example, TFTs with high thresholds Vth, includes a complementary generator unit (11) driven by a first power supply (VCC) having an amplitude voltage equal to the amplitude voltage of... Agent: Robert J. Depke Lewis T. Steadman

20070063758 - Voltage divider and method for minimizing higher than rated voltages: A voltage divider circuit can be realized by dividing a higher than rated operating voltage across a plurality of MOS transistors. The voltage divider circuit can be used for a wide variety of ratios of low and high operating voltages. Only one gate input voltage is needed, minimizing power dissipation,... Agent: Honeywell International Inc.

20070063760 - Charge pump: A charge pump comprises a single voltage multiplier stage (1) which converts an input voltage (VDD) into an output voltage (Vo) under control of a clock signal (Q, Qn; CLKO). An oscillator (2) receives the input voltage (VDD) to generate the clock signal (Q, Qn; CLKO) having a repetition period... Agent: Philips Intellectual Property & Standards

20070063761 - Charge pump system with smooth voltage output: A method and system is disclosed for an improved charge pump system. The system comprises one or more charge pump devices for providing an output voltage, a ring oscillator coupled with the charge pump devices for providing an oscillator output, and a multiple level detection device for detecting the output... Agent: Howard Chen, Preston Gates & Ellis LLP

20070063762 - Semiconductor device with charge pump booster circuit: Provided is a charge pump booster circuit capable of outputting desired boosted voltage that is not limited to an integral multiple of input voltage and further outputting stable boosted voltage even if a load fluctuates. In the charge pump booster circuit, gate voltage of a transistor for pumping is controlled... Agent: Brinks Hofer Gilson & Lione

20070063763 - Source transistor configurations and control methods: Source transistor configurations are described for reducing leakage and delay within integrated circuits. Virtual power and ground nodes are supported with the use of stacked transistor configurations, such as a two transistor stack between a first virtual supply connection and VSS, and a second virtual supply connection and VDD. Gate... Agent: John P. O'banion O'banion & Ritchey LLP

20070057697 - Apparatus and method for verifying glitch-free operation of a multiplexer: An apparatus and method for verifying glitch-free operation of a multiplexer are provided. The apparatus includes a circuit having a plurality of flip-flop elements that receive as inputs the plurality of clock signals that are inputs to the multiplexer, and a corresponding synchronized output signal of a decoder generated based... Agent: Ibm Corp. (wip) C/o Walder Intellectual Property Law, P.C.

20070057698 - Dynamic and differential cmos logic with signal-independent power consumption to withstand differential power analysis: A dynamic and differential CMOS logic style is disclosed in which a gate uses a fixed amount of energy per evaluation event. The gate switches its output at every event and loads a constant capacitance. The logic style is a Dynamic and Differential Logic (DDL) style. The DDL style logic... Agent: Knobbe Martens Olson & Bear LLP

20070057699 - Multi-channel integrated circuit: A multi-channel integrated circuit is provided in which each channel has an analog section and a digital section. Each channel of the readout chip employs low noise charge sensitive amplifier at its input followed by other circuitry such as shaper, pole-zero, peak hold, different comparators, buffers and digital control and... Agent: Snider & Associates

20070057700 - Cam cells and cam matrix made up of a network of such memory cells: A content addressable memory (CAM) includes first and second memory circuits and a comparison circuit. The first memory circuit includes first and second sets of transistors for the storage of first and second compare data. The second memory circuit includes first and second sets of transistors for the storage of... Agent: Allen, Dyer, Doppelt, Milbrath & Gilchrist P.A.

20070057701 - High-performance, low-noise reference generators: Generators are provided for supplying reference signals that are especially suited to signal conditioning systems such as analog-to-digital converters. They generate reference signals with low output impedances that reduce spurious signals and shorten recovery times. Filters are included to decouple reference structures and thereby reduce noise signals, reduce ringing and... Agent: Koppel, Patrick & Heybl

20070057702 - Output buffer circuit: Disclosed is an output buffer circuit including a first differential transistor pair for differentially receiving a data signal from a differential input pair; and a second differential transistor pair for differentially receiving an emphasis data signal from another differential input pair; a pair of output resistor circuits via which the... Agent: Foley And Lardner LLP Suite 500

20070057703 - Input buffer for cmos integrated circuits: An input buffer for CMOS integrated circuits using sub-micron CMOS technology is affected by the presence of high voltage between various ports of a device. An improvement for such a buffer provides an input voltage limiting circuit making the device mode tolerant to high voltages while using low voltage tolerant... Agent: Jenkens & Gilchrist, PC

20070057704 - Motor drive circuit: Two systems consisting of an on-off control section corresponding to the saturation drive system and a constant voltage control section corresponding to the constant voltage drive system are provided as a circuit for controlling the conduction state of a transistor QP11 provided at the output section. The constant voltage unit... Agent: Oliff & Berridge, PLC

20070057705 - Output buffer circuit: When a first signal is switched from an L level to an H level and a second signal is switched from an H level to an L level, and a first constant current source cannot follow the switching immediately thereafter and has not yet been switched, a first node remains... Agent: Buchanan, Ingersoll & Rooney PC

20070057706 - Multiphase resonant pulse generators: A multiphase resonant pulse generator (74) has N groups of N−1 switches (44,46,48) which, when activated, form N paths from a power supply ((Vdc)) to ground or a reference voltage. Here N is a positive integer greater than 2. Each of the paths includes an inductance (38,40,42) and N−1 switches.... Agent: Mcdermott Will & Emery LLP

20070057707 - Triangular wave generation circuit: A first constant-current source supplies a charging current to a second terminal of a first capacitor in which a first terminal is grounded. A first terminal of a second capacitor is grounded, and a first switch is provided between the second terminal of the first capacitor and a second terminal... Agent: Cantor Colburn, LLP

20070057709 - Clock generation circuit and clock generation method: A clock generation circuit and a clock generation method are provided, which are capable of spread spectrum clock generation and accurate phase control of a reference clock signal and an output clock signal. To this end, an input divider unit 70 divides an input clock signal CLKR by 50 to... Agent: Arent Fox PLLC

20070057708 - False lock detection mechanism for use in a delay locked loop circuit: The delay locked loop circuit includes a charge pump circuit that may charge and discharge in response to an assertion of an up signal and a down signal, respectively. The delay locked loop circuit also includes a detection circuit that may assert the up signal indicating an occurrence of a... Agent: Meyertons, Hood, Kivlin, Kowert & Goetzel, P.C.

20070057710 - Timing adjustment circuit and method thereof: A timing adjustment circuit and method thereof are disclosed. The timing adjustment circuit at least consists of a second timing adjustment unit, a multistage sample circuit, and a decision circuit for adjusting received timing of an output signal transmitted by a first chip and received by a second chip. The... Agent: Rosenberg, Klein & Lee

20070057711 - Slewing rate adjustment circuit: Disclosed is a slew rate adjustment circuit for adjusting the slew rate of an output buffer having an output transistor and a pre-transistor in a preceding stage of the output transistor which includes a resistance adjustment circuit and a resistance adjustment circuit. The resistance adjustment circuit and the resistance adjustment... Agent: Mcginn Intellectual Property Law Group, PLLC

20070057712 - High frequency divider state correction circuit: The present invention provides for a self-correcting state circuit. A first flip flop is configured to receive a clock input and a first data input, and to generate a first output in response to the clock input and the first data input. A second flip flop is coupled to the... Agent: Ibm Corporation (cs) C/o Carr LLP

20070057713 - Non-latching enveloping curves generator: An enveloping curves generator is disclosed that guarantees that one curve will envelop or overlap another when both are traversing from one logic level to another, and where the other overlaps the first when both traversing the other direction. In one case, a steering FET controlled by an input signal... Agent: Cesari And Mckenna, LLP

20070057714 - Method and device for generating an output signal having a predetermined phase shift with respect to an input signal: An output signal is generated with a predetermined phase shift with respect to an input signal using a closed loop control. The input and output signal of the closed loop control are logically combined in accordance with first and second combinatory logic to generate first and second control signals. The... Agent: Brinks Hofer Gilson & Lione Infineon

20070057715 - System and method for detecting processing speed of integrated circuit: A system for detecting the processing speed of an integrated circuit (IC) includes a flip-flop, a delay module, and a judge unit. The flip-flop receives a clock signal as a trigger signal and generates an inverted output signal. The delay module receives the inverted output signal, adjusts the delay time... Agent: Birch Stewart Kolasch & Birch

20070057716 - Power supply voltage detection circuitry and methods for use of the same: Power detection circuitry that provides a substantially constant trip-point is provided. The circuitry is immune to temperature and process variations, thus preventing premature or delayed enablement of utilization circuitry (e.g., memory). In addition, the trip-point remains constant during both slow and fast power up and power down conditions. This may... Agent: Fish & NeaveIPGroup Ropes & Gray LLP

20070057717 - Circuits for generating reference current and bias voltages, and bias circuit using the same: A circuit for generating a reference current comprises: a first current mirror configured to current-mirror based on a second current, so as to generate a first current that is substantially in inverse proportion to a variation of a power supply voltage; a current compensation unit configured to remove a variation... Agent: Mills & Onello LLP

20070057718 - Method and apparatus for improving the performance of pilot symbol assisted receivers in the presence of narrowband interference: A method for reducing interference from at least one narrowband interferer in a pilot symbol assisted receiver (10) includes the steps of; receiving a stream of received data, passing the stream of received data through an adaptive filter that reduces interference from any narrowband interferer, passing the filtered data through... Agent: Dann, Dorfman, Herrell & Skillman

20070057719 - Analog filter circuit and adjustment method thereof: An analog filter circuit in which filter characteristic deviation can be adjusted with simple circuitry and its adjustment method can be provided. The analog filter circuit includes a low pass filter and a high pass filter and output signals of both filters are input to a comparison and adjustment section... Agent: Arent Fox PLLC

20070052449 - Deglitch circuit: A deglitch circuit capable of removing noise with low power consumption. Voltage is input to a first inverter, connected to a power supply line via a first current source and grounded via a second current source. The first inverter is grounded via a capacitor and connected to first and second... Agent: Freescale Semiconductor, Inc. Law Department

20070052450 - Current feedback amplifiers: Current feedback amplifiers circuits that generate common mode (CM) and/or differential mode (DM) currents are provided herein. This description is not intended to be a complete description of, or limit the scope of, the invention. Other features, aspects, and objects of the invention can be obtained from a review of... Agent: Fliesler Meyer LLP

20070052451 - Differential inverter circuit: An improved differential inverter comprising a differential inverter having a differential input for receiving a first input signal and a second input signal, said inverter further comprising a differential control input for receiving a first control signal and a second control signal. The improved differential inverter further comprises a differential... Agent: Philips Intellectual Property & Standards

20070052452 - Sample/hold circuit module: A sample/hold circuit module. The sample/hold circuit module comprises a sample/hold circuit, an S/H controller, a pass transistor, and a high voltage generator. The sample/hold circuit comprises a capacitor and a sampling switch. The capacitor has a first electrode coupled to a first fixed voltage and a second electrode coupled... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070052453 - Method and apparatus for monitoring and controlling the thermal environment and operating conditions of an integrated circuit: Logic included in an IC monitors values of parameters that may affect operation of the IC, such as, for example, supply voltage (VDD), junction temperature (TJUNC) and the frequency of a ring oscillator on the IC. In response to the monitored values, the logic in the IC changes, if necessary,... Agent: Avago Technologies, Ltd.

20070052455 - Low-power multi-level pulse amplitude modulation driver and semiconductor device having the driver: A low-power multi-level pulse amplitude modulation (PAM) driver, and a semiconductor device having the same, in which the multi (M)-level PAM driver includes a load unit, first and second current sources, a pair of first input transistors, a pair of second input transistors, and a current source controller, where M... Agent: F. Chau & Associates, Llc

20070052454 - Technique for determining a load current: An integrated driver with improved load current sense capability includes a first transistor, a first amplifier, a second transistor, a third transistor, a second amplifier and a fourth transistor. The integrated driver allows for significantly better fault handling capability, provides accurate thermal and current sensing capability and reduces I/O pin... Agent: Delphi Technologies, Inc.

20070052456 - Agc circuit for the reduction of harmonics in the drive signal: A drive circuit apparatus for use in generating a drive signal for energizing an actuator about a natural resonant frequency is disclosed. The circuit has a counter that generates a count sequence derived from a drive sense signal. Additionally, a demodulator is further coupled to the counter and generates a... Agent: Moore & Hansen, Pllp

20070052458 - Frequency divider circuit with controllable frequency division ratio and method for frequency division in a frequency divider circuit: A frequency divider circuit is disclosed with at least one push-pull divider with adjustable division ratio and a connected converter device. The circuit converts a clock signal delivered by a push-pull divider into a single-ended signal. A first and a second single-ended divider are connected to the output of the... Agent: Eschweiler & Associates, Llc National City Bank Building

20070052457 - Frequency-divider circuit arrangement: A frequency-divider circuit arrangement having a power supply, a first clock signal, a second clock signal, a first switch unit, a first capacitance which is connected downstream from the first switch unit is disclosed. A second switch unit is connected downstream from the first capacitance and is controlled by the... Agent: Dicke, Billig & Czaja, P.l.l.c.

20070052459 - Multiphased triangular wave oscillating circuit and switching regulator using it: To oscillate and output multiphased triangular waves with a designed waveform shape, wave crest value, and phase relationship. This multiphased triangular wave oscillating circuit has two triangular wave generating circuits 10A and 10B for generating two phased triangular waves A and B with phases opposite each other, a middle point... Agent: Texas Instruments Incorporated

20070052460 - Statically controlled clock source generator for vcdl clock phase trimming: The present invention addresses the generation of a controlled clock source for use in trimming VCDL delay line output clocks. In this trimming process, adjustments are made for static variations in these output clocks. The invention's use of a controlled clock source eliminates the need for this trimming process to... Agent: Synnestvedt & Lechner LLP-agere

20070052461 - Linear charger where the material temperature directly affects the circuit thermal control: Methods and apparatus are disclosed for protecting circuits from damages caused by elevated temperatures. Presented embodiments illustrate IC thermal protection circuits that shut down power delivery circuits when the circuit temperature reaches a predefined upper threshold and restart the circuit when the circuit cools down to a predefined lower threshold.... Agent: Perkins Coie LLP Patent-sea

20070052462 - Control signal generation circuit and battery management system using the same: A control signal generating circuit used in a battery management system may stably generate a control signal. The control signal generating circuit includes a first signal line transmitting a first control signal having an on-level or an off-level, a second signal line transmitting a second control signal having an on-level... Agent: Stein, Mcewen & Bui, LLP

20070052463 - Method and apparatus for sigma-delta delay control in a delay-locked-loop: Methods and apparatus are provided for sigma-delta delay control in a Delay-Locked-Loop that employs a delay line to generate a clock signal based on a reference signal. A first value is generated if a clock signal has a time lead relative to a reference signal; and a second value is... Agent: Ryan, Mason & Lewis, LLP

20070052464 - Method of estimating an intersection between at least two continuous signal representations: The invention relates to a method of estimating an intersection between at least two continuous signal representations (SR1, SR2) in a pulse width modulator, at least one of said continuous signal representations (SR1, SR2) being non-linear, said method comprising the step of providing an intersection estimate (CPE) between said at... Agent: Cantor Colburn, LLP

20070052465 - Schmitt trigger with electrostatic discharge (esd) protection: An Schmitt trigger with electrostatic discharge protection includes a first PMOS, a second PMOS, a first NMOS, and a second NMOS, which are connected in series and each of which has a gate coupled to an input terminal. The drain of the second PMOS is coupled to an output terminal.... Agent: North America Intellectual Property Corporation

20070052466 - Flip-flop with improved operating speed: A flip-flop with an improved operating speed is disclosed. The flip-flop includes a switch unit, a latch unit and a reset controller. The switch unit transfers data to a first node in response to a clock signal. The latch unit latches the data apparent at the first node at a... Agent: Volentine Francos, & Whitt Pllc

20070052467 - Current-controlled cmos (c3mos) fully differential integrated delay cell with variable delay and high bandwidth: Current-controlled CMOS (C3MOS) fully differential integrated delay cell with variable delay and high bandwidth. A novel implementation includes a wideband differential transistor pair and a cross-coupled differential transistor pair. The wideband differential transistor pair can be implemented with appropriate input and output impedances to extend its bandwidth for use in... Agent: Garlick Harrison & Markison

20070052468 - Shift down level shifter: A shift down-level shifter used with a memory negative word line architecture prevents current flow between a positive bias voltage and a negative bias voltage when the input signal is at circuit ground. The output circuit of the shift down-level shifter comprises two transistors connecting a positive voltage and a... Agent: Stephen B. Ackerman

20070052469 - Mixer-system with gain-blocks and switches: Mixer-systems comprising gain-blocks (1-4) and switches (5-8) have a flexibility depending upon their configuration (insight) and are made more flexible (basic idea) by supplying data input signals to the gain-blocks (1-4) and oscillation signals to the switches (5-6) for switching couplings between the gain-blocks (1-4). A switch (5-6) comprises a... Agent: Philips Intellectual Property & Standards

20070052470 - Switching voltage supply of voltage domain of semiconductor circuit: A method of switching on a voltage supply of a voltage domain of a semiconductor circuit includes switching, initially, a first switchable element, via which elements of the voltage domain are connected to a supply voltage of the semiconductor circuit, to a conductive state. The method includes switching, after a... Agent: Dicke, Billig & Czaja, P.l.l.c.

20070052471 - Power supply apprartus: The invention relate to a power supply apparatus operating on the charge pump principle, comprising multiple regulators and three boosting capacitors switched in a switch matrix consisting of nine switches. A control circuit is provided capable of controlling the switches so that the charge pump is changed over between charging... Agent: Shek-wai Ng

20070052472 - Systems and methods for generating reference voltages: Systems and methods for generating reference voltages are provided. A representative system comprises a resistor circuit; a first switch coupled between a first end of the resistor circuit and a first power source; a second switch coupled between the first end of the resistor circuit and a second power source;... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070052473 - Perfectly curvature corrected bandgap reference: In one embodiment, a bandgap voltage reference generating circuit is configured to generate a reference voltage, and may comprise a first PN-junction whose base-emitter voltage (VBE) exhibits a curvature with respect to temperature, where a current conducted by the first PN-junction is proportional to absolute temperature (PTAT). The voltage reference... Agent: Meyertons, Hood, Kivlin, Kowert & Goetzel, P.c.

20070046337 - Comparator circuit and semiconductor apparatus: A comparator circuit includes a first and a second PMOS transistors having sources connected to a first power supply and drains connected to a first node, NMOS transistors having sources connected to a second power supply and drains connected to the first node, a third and a fourth PMOS transistors... Agent: Sughrue Mion, PLLC

20070046338 - Buffer circuit with multiple voltage range: A buffer circuit operative at multiple power supply voltage levels includes first and second buffers, the first buffer being configured for operation with a first voltage source and the second buffer being operative with a second voltage source. The buffer circuit further includes a controllable isolation circuit. An output of... Agent: Ryan, Mason & Lewis, LLP

20070046339 - Output circuit: A drain of a NMOS 32 of a canceling circuit 30 is connected to an output node NO to set the source of the above NMOS32 to floating-state. Furthermore, the gate of the NMOS 32 is provided with a signal SB being inverted by an inverter 31. By the above... Agent: Nixon Peabody, LLP

20070046340 - Clock frequency divider circuit and method of dividing clock frequency: A clock frequency divider circuit and method of dividing a clock frequency are provided. The clock frequency divider circuit includes a first flip-flop circuit, a second flip-flop circuit, a third flip-flop circuit, a first logic control unit and a second logic control unit, wherein the first flip-flop circuit has two... Agent: Jianq Chyun Intellectual Property Office

20070046341 - Method and apparatus for generating a power on reset with a low temperature coefficient: Methods and apparatuses for generating a power-on-reset signal that is substantially independent of temperature change are disclosed. A reset circuit comprises a voltage generator, a first resistance element, a current generator, and a comparator. The voltage generator is configured for generating a first voltage signal having a negative temperature coefficient.... Agent: Trask Britt, P.C./ Micron Technology

20070046342 - Semiconductor integrated circuit: The present invention is directed to assure an initial state of a circuit until a power supply voltage is stabilized at the time of power-on and to prevent an output circuit of an external input/output buffer circuit from performing erroneous operation at the time of setting a predetermined register value... Agent: Miles & Stockbridge PC

20070046343 - Pll with controlled vco bias: In some embodiments, a PLL with an output to provide a PLL output clock at a target frequency is provided. The PLL comprises a VCO to generate a clock to be used to generate the PLL output clock. Also provided is circuitry to maintain the VCO's bias level at a... Agent: Blakely Sokoloff Taylor & Zafman

20070046346 - Clock controller with integrated dll and dcc: A clock controller for use with an off-chip driver and including a first delay element, a second delay element, a restore circuit, and an adjustment circuit. The clock controller includes a node receiving a reference clock represented by a least one clock signal. The first delay element is configured to... Agent: Dicke, Billig & Czaja, P.l.l.c.

20070046347 - Delay locked loop: A DLL for reducing jitter during a high frequency operation by separately controlling a coarse delay and a fine delay. The DLL includes a multiplexing unit for selectively outputting one of the rising clock and the falling clock; a first delay line for generating a first internal clock and a... Agent: Blakely Sokoloff Taylor & Zafman

20070046344 - Delay locked loop using a fifo circuit to synchronize between blender and coarse delay control signals: Embodiments of the present invention generally provide improved techniques and circuit configurations for a delay-locked loop (DLL) circuit. In one embodiment, a first phase difference between an input clock signal and an output clock signal is measured. Based on the first phase difference, a first phase adjustment setting is stored... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Infineon / Qimonda

20070046348 - Delay locked loop with common counter and method thereof: A delay locked loop circuit for delaying an input clock to lock a delay clock. The delay locked loop includes a frequency divider for dividing a frequency of the input clock by a number N to obtain a frequency-divided clock, a plurality of delay components for delaying the input clock... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070046345 - In-loop duty corrector delay-locked loop for multiphase clock generation: A delay-locked loop (DLL) employs an in-loop duty cycle corrector (DCC) to provide accurate multiphase clock generation with 50% duty cycle. Each delay cell can advantageously provide both delay and duty cycle correction functionality. In one embodiment, delay correction can precede duty cycle correction. The bandwidths of the DCC and... Agent: Bever Hoffman & Harms, LLP Tri-valley Office

20070046349 - Phase controllable multichannel signal generator: A signal generator can control phase relationship between output signals of the channels without stopping clocks provided to the channels to enable the circuit operation fast. First and second channels 20 and 22 have signal generation blocks 10 and 12 that have clock phase shift circuits 26 and 28, memories,... Agent: Thomas F. Lenihan Tektronix, Inc.

20070046350 - Pre-emphasis circuit including slew rate controllable buffer: A pre-emphasis circuit capable of controlling the slew rate of a signal output from a buffer that transfers the output signal to an output driver to increase the range of a controllable voltage step includes a first buffer, a second buffer, and an output driver. The first buffer buffers first... Agent: F. Chau & Associates, LLC

20070046351 - Duty cycle corrector: A duty cycle corrector including a restore circuit configured to receive a differential input clock and a differential feedback clock each having crossings of a first type and a second type and to provide a differential output clock having crossing of the first type based on differential input clock crossings... Agent: Dicke, Billig & Czaja, P.l.l.c.

20070046352 - Flip-flop implemented with metal-oxide semiconductors using a single low-voltage power supply and control method thereof: The present invention discloses a flip-flop implemented with metal-oxide semiconductors using a single low-voltage power supply and a control method thereof, wherein an external control signal is input to a power switch in order to turn on the power switch for an active mode or to turn off the power... Agent: Rosenberg, Klein & Lee

20070046353 - Hybrid control for discharge lamps: Control methods and apparatus are disclosed for operating an inverter at resonant mode, where the inverter adapts its frequency to the resonant tank characteristics before a lamp is struck, and operates at fixed frequency after the lamp is struck. Disclosed embodiments combine the advantages of operation in fixed mode as... Agent: Perkins Coie LLP Patent-sea

20070046354 - Delay adjustment circuit and synchronous semiconductor device having the delay adjustment circuit: Disclosed is a delay adjustment circuit including a first set of transistors, which are connected between a PMOS transistor forming an inverter and a power supply in parallel and have gates supplied with control signals, respectively, a second set of transistors which are connected between an NMOS transistor forming the... Agent: Foley And Lardner LLP Suite 500

20070046355 - Method and apparatus for digital phase generation for high frequency clock applications: An apparatus and method for generating phase-related clocks are disclosed. A clock input is delayed by an alignment magnitude to generate a first phase signal. The first phase signal is delayed by the phase alignment magnitude to generate a first phase delay signal. The clock input is delayed by a... Agent: Trask Britt, P.C./ Micron Technology

20070046356 - Adaptive dc offset compensation apparatus and method thereof: Provided are a direct current (DC) offset compensation apparatus and a method thereof. A DC offset compensation apparatus comprises an offset detection block detecting a DC offset, an offset compensation block operating according to an output signal of the offset detection block, and an offset compensation amplifying block controlled according... Agent: Foley And Lardner LLP Suite 500

20070046357 - Level shift circuit and semiconductor device: A level shift circuit for sustaining the activation and inactivation response of a transistor with respect to an input signal in a preferable manner. The level shift circuit includes a shift circuit for converting an input signal having a first voltage to an output signal having a second voltage that... Agent: Arent Fox PLLC

20070046358 - Quick turn on apparatus and method for a nmosfet switch: A quick turn on apparatus and method for a NMOSFET switch are used to maintain the gate voltage of the NMOSFET switch non-zero but not enough to turn on the NMOSFET switch, such that the NMOSFET switch turns on more quickly when it is to be turned on. Seamless transition... Agent: Rosenberg, Klein & Lee

20070046359 - Apparatus and method for effecting switching of an input signal by a switching transistor: An apparatus switching an input signal by a switching transistor in response to a clock includes: (a) A capacitor. (b) A charging circuit coupled for charging the capacitor with a supply voltage in response to the clock. (c) A switching circuit coupled with the capacitor and configured for coupling the... Agent: Texas Instruments Incorporated

20070046360 - Electronic array having nodes and methods: An electronic network comprises a plurality of nodes that each comprise a current input and a current output, and at least one transistor arranged as a first current mirror and a second current mirror. The first and the second current mirrors are complementary to each other such that an output... Agent: Townsend And Townsend And Crew, LLP

20070046361 - Circuitry and method for programming an electrically programmable fuse: Circuitry that includes a voltage controller (224) for providing a variable gate signal (220) for controlling the gate of a programming transistor (212) used in conjunction with programming an electrically programmable fuse (“eFuse”) (204) of an integrated circuit (200). The voltage controller adjusts the gate signal depending upon whether the... Agent: Downs Rachlin Martin PLLC

20070046362 - Adaptive voltage control and body bias for performance an energy optimization: A device for adaptively controlling a voltage supplied to circuitry in close proximity to the device, comprising a processing module and a first tracking element coupled to the processing module. The first tracking element produces a first value indicative of a first estimated speed associated with the circuitry. The device... Agent: Texas Instruments Incorporated

20070046364 - Constant current circuit: In CMOS processing, there may be a case in which a resistance element, such as a poly-silicon resistance, or the like, may be formed which has negative temperature characteristics, that is, the characteristics opposite from the characteristics of a typical resistance element. In a constant current circuit using this resistance... Agent: Oliff & Berridge, PLC

20070046363 - Method and apparatus for generating a variable output voltage from a bandgap reference: A method and apparatus for generating a variable output voltage from a voltage reference circuit is disclosed. A voltage reference circuit includes a first voltage generator configured for generating a first voltage signal having a negative temperature coefficient and a second voltage generator configured for generating a second voltage signal... Agent: Trask Britt, P.C./ Micron Technology

20070046365 - Bias circuit having transistors that selectively provide current that controls generation of bias voltage: A bias circuit, which generates a bias voltage, has a first MOS transistor coupled between a first reference voltage terminal and a voltage dividing node and a second MOS transistor coupled in parallel with the first MOS transistor. The first MOS transistor may have a first ON-state resistance, and the... Agent: Volentine Francos, & Whitt PLLC

20070046366 - Tunable resonator for use in active-rc continuous-time filters: An integrated circuit (IC) resonator in which resonator parameters potentially affected by IC fabrication processes are correctable after fabrication. Resonance frequency tuning is effected by forming each feedback capacitor in a pair of integrator circuits to include a variable capacitance device, such as a varactor diode. A tuning signal is... Agent: Tarolli, Sundheim, Covell & Tummino L.L.P.