Miscellaneous active electrical nonlinear devices, circuits, and systems inventions 01/07

20070018695 - Large supply range differential line driver: A differential transmission line driver with supplemental current sources that overcome switching anomalies and EMU issues when the logic state of the driver is switching. During a logic transition, a current source, that is directed to the output of the driver, may be prevented from delivering its current. The present... Agent: Cesari And Mckenna, LLP

20070018696 - Transmitting circuit and semiconductor integrated circuit: A transmitting circuit includes an internal circuit, a first dividing circuit, a second dividing circuit, a delay circuit, a first switching circuit, and a second switching circuit. The first dividing circuit is coupled between a first power voltage and the internal circuit, and the second dividing circuit is coupled between... Agent: F. Chau & Associates, LLC

20070018697 - Double frequency signal generator: A double frequency signal generator to which a synchronization signal having a duty cycle of 1% to 999% is inputted. The synchronization signal is used for triggering of a switching component at positive and negative edges to generate a triangular-wave signal. An average of voltages of the triangular-wave signal is... Agent: Hdsl

20070018700 - Charge pump control circuit and control method thereof: A charge pump control circuit and a control method for controlling charge pumps are disclosed. The output terminal of the charge pump is coupled to a load circuit. The charge pump control circuit includes a detecting and controlling circuit and a controlled oscillator. The detecting and controlling circuit is used... Agent: Jianq Chyun Intellectual Property Office

20070018698 - Method and apparatus for implementing fault tolerant phase locked loop (pll): A method and apparatus are provided for implementing a fault tolerant phase locked loop (PLL). The PLL circuit includes a divide by N circuit defined by a plurality of sub-divide by N functions, each providing a feedback frequency signal applied to a voter circuit. The voter circuit provides an output... Agent: Ibm Corporation RochesterIPLaw Dept 917

20070018699 - Partial cascode phase locked loop architecture: Various embodiments for a partial cascode phase locked loop architecture are described. In one embodiment, an apparatus may include a phase locked loop circuit having a plurality of partial cascode circuits. The plurality of partial cascode circuits may be arranged to reduce phase noise from a ground power supply voltage... Agent: Tyco Electronics

20070018701 - Charge pump apparatus, system, and method: Apparatus, system, and method including a single common node bias voltage; at least a first current path to drive a bias current based on the single common node bias voltage; at least a first current mirror to mirror the bias current in a second current path; and an output current... Agent: Tyco Electronics Corporation

20070018702 - Delay-locked loop circuit with variable bias voltages and method of clock synchronization for a semiconductor memory device: A delay-locked loop circuit comprising a variable voltage generator and a delay-locked loop. The variable voltage generator is configured to generate a variable bias voltage signal in response to a standby signal. The variable bias voltage signal has differing voltage levels according to operation modes. The operation modes include a... Agent: F. Chau & Associates, LLC

20070018703 - Jitter tolerance testing apparatus, systems, and methods: Apparatus, systems, methods, and articles may operate to move an output phase of a clock phase adjustment device associated with a master clock through a plurality of phase shifts relative to a phase of the master clock. A data integrity test may be performed on a serial data receive circuit... Agent: Schwegman, Lundberg, Woessner & Kluth, P.A.

20070018704 - Clock data recovery circuit capable of generating clock signal synchronized with data signal: PD detects a phase difference between DATA and VDL output from VDL. Code Operator detects a value of a control code corresponding to a delay equal to one period of an output clock. Then, when a delay amount of VDL exceeds one period of a clock during synchronization of the... Agent: Buchanan, Ingersoll & Rooney PC

20070018705 - Phase frequency detector with a novel d flip flop: Methods, systems and components for use with or as a phase frequency detector. The phase frequency detector stretches its output pulse, allowing the detector to operate in a more linear region. As part of the invention, a new configuration for a D type flip flop is also disclosed. In one... Agent: Cassan Maclean

20070018706 - Flip-flop circuit: A scan flip-flop circuit including an input section employing a dynamic circuit and an output section employing a static circuit, capable of latching in data within a period of a pulse width that is shorter than the clock cycle, wherein only three N-type transistors are connected in series in the... Agent: Mcdermott Will & Emery LLP

20070018707 - High frequency balanced pahse interpolator: A phase interpolation system includes an input stage that provides first and second modulated input signals having selected first and second relative phase angles. A weighting system is configured to steer a first portion of the first modulated input signal to an output and a second portion of the first... Agent: Texas Instruments Incorporated

20070018708 - Method and apparatus for determining optimal delay time and computer-readable storage medium storing optimal delay time determining program: A method of and an apparatus for determining an optimal delay time and a computer-readable storage medium storing an optimal delay time determining program. By determining an optimal delay time between data packet transmissions from a master to a slave through a serial data line, speed reduction and overload of... Agent: Stein, Mcewen & Bui, LLP

20070018709 - Variable impedance circuit and apparatus comprising said variable impedance circuit: A variable impedance circuit includes at least one fixed resistance and a plurality of transistors between a first and a second terminal. The transistors belonging to the plurality of transistors are arranged parallel to one another and parallel to the resistance and are controllable by a plurality of control signals... Agent: Seed Intellectual Property Law Group PLLC

20070018710 - Level shifter circuit of semiconductor memory device: A level shifter circuit of a semiconductor memory device prevents a leakage current from being generated in a deep power down mode. The level shifter circuit comprises: a first NMOS transistor connected between a first node and a ground voltage terminal, wherein an input signal, which has a voltage level... Agent: Mills & Onello LLP

20070018711 - Power supply circuit: A power supply circuit includes first and second power supply circuits. The first power supply circuit has a first voltage generation circuit and the second power supply circuit has a second voltage generation circuit and an operational amplifier. When a load is in a low power consumption mode, only the... Agent: Posz Law Group, PLC

20070018712 - Pvt variation detection and compensation circuit: A compensation circuit and a method for compensating for process, voltage and temperature (PVT) variations in an integrated circuit (IC). The IC includes several functional modules, each of which includes a set of functional units, and generates an output signal in response to an input signal. The compensation circuit includes... Agent: Freescale Semiconductor, Inc. Law Department

20070018713 - Pvt variation detection and compensation circuit: A compensation circuit and a method for detecting and compensating for process, voltage, and temperature (PVT) variations in an integrated circuit. The integrated circuit includes plural logic modules that include PMOS transistors and NMOS transistors. The compensation circuit includes first and second functional modules, which generate first and second calibration... Agent: Freescale Semiconductor, Inc. Law Department

20070018714 - Temperature sensor system and method: A method and system for sensing the temperature of an integrated circuit are presented. The method compares a first current that is proportional to a temperature reading of the integrated circuit to a reference current. While the first current is greater than the reference current, a counter is incremented, and... Agent: Toler Schaffer, LLP

20070018715 - Clocked standby mode with maximum clock frequency: A method and apparatus for controlling a voltage generator of a memory device are provided. In one embodiment, a first clock signal and a second clock signal are provided. The voltage generator is selectively enabled in conjunction with the first clock signal when a period of the first clock signal... Agent: Patterson & Sheridan, LLP Gero Mcclellan / Infineon / Qimonda

20070018716 - Circuit arrangement having a transistor component and a freewheeling element: A circuit arrangement configured to drive a load is disclosed herein. The circuit arrangement comprises a first and a second supply potential terminal for application of a first supply potential and a second supply potential. A load terminal is provided between the first and second supply potential for connection of... Agent: Maginot, Moore & Beck Chase Tower

20070013414 - 0th droop detector architecture and implementation: A voltage droop detector captures the very high-frequency noise on the power grid of a load, such as a microprocessor. The droop detector includes twin circuits, one of which receives the voltage from the power grid of the load, the other of which receives a filtered voltage. A 0th droop,... Agent: Carrie A. Boone, P.C.

20070013415 - Comparator circuit with built-in programmable floating gate voltage reference: A circuit for setting a reference voltage in a floating gate circuit is configured as a precise voltage comparator circuit with a built-in programmable voltage reference. Once the one or more floating gates in the floating gate circuit are set during the a SET operation, the floating gate circuit is... Agent: Nixon Peabody, LLP

20070013417 - Sample-and-hold circuits having reduced channel conductance variation and methods of operation thereof: An electronic device, such as a sample-and-hold circuit, includes a field effect transistor (FET), a capacitor, and a voltage offset circuit. The FET is configured to receive a signal at a first terminal thereof and selectively provide the signal to a second terminal thereof responsive to a switching signal at... Agent: Myers Bigel Sibley & Sajovec

20070013416 - Sample-and-hold device: A sample-and-hold device including first and second capacitors, first and second switches, amplifier and feedback network is provided. The amplifier includes first and second input stages, output stage and switchable bias current source. The first switch and the first capacitor are coupled in series between input signal and first voltage,... Agent: Jianq Chyun Intellectual Property Office

20070013418 - Methods and apparatus for dividing a clock signal: There is provided a true single phase logic clock divider that is configured to divide a clock signal by increments of two, three, four, or six. Because the true single phase logic clock divider is based on true single phase logic instead of static logic, the true single phase logic... Agent: Michael G. Fletcher Fletcher Yoder

20070013419 - Central coordinator selection, handover, backup and failure recovery: The embodiments of the present invention provide methods, systems, and devices for improving network management in a centralized network, which typically includes a central coordinator (CCO) that manages and schedules activities within the network. The embodiments of the invention provide a manner of selecting a CCO, including a backup CCO,... Agent: Michael Blaine Brooks, PC

20070013420 - Internal voltage generator and internal clock generator including the same, and internal voltage generating method thereof: An internal voltage generator that generates an internal voltage for a Delay Locked Loop (DLL) and an internal clock generator including the same, and an internal voltage generating method for a DLL. The internal voltage generator includes a standby voltage generator that generates the DLL internal voltage as a reference... Agent: Mayer, Brown, Rowe & Maw LLP

20070013421 - Energy efficient clock deskew systems and methods: Systems and methods for active clock deskew are provided. The disclosed systems/methods advantageously achieve desirable clock deskew at reduced power levels by employing a resistance-based distributed clock deskew technique. The disclosed technique has broad commercial/industrial applicability, e.g., in VLSI/ULSI chips, such as microprocessors, digital signal processing systems (DSPs), integrated circuits,... Agent: Attn: Basam E. Nabulsi Mccarter & English, LLP

20070013422 - Clock pulse width control circuit: In one embodiment, a clock pulse width control circuit, comprises a plurality of timer circuits to generate a corresponding plurality of delayed pulse signals from an input clock signal, a corresponding plurality of AND gates, each AND gate generating an output signal from a delayed pulse signal and the input... Agent: Hewlett Packard Company

20070013423 - Duty cycle correction device: Disclosed is a duty cycle correction device for correcting a duty cycle of a clock signal output from a delay locked loop circuit. The duty cycle correction device includes a mixer for mixing phases of the first and second clock signals, thereby outputting a first signal, a phase splitter receiving... Agent: Ladas & Parry LLP

20070013424 - Differential dual-edge triggered multiplexer flip-flop and method: A differential dual-edge triggered multiplexer flip-flop configured and operated to capture a first data signal on one edge of the clock and a second data signal on the other clock edge. By so doing, the output data rate of such a flip-flop is twice that of the input data rate... Agent: Epson Research And Development Inc Intellectual Property Dept

20070013425 - Lower minimum retention voltage storage elements: The present invention relates to integrated circuit storage element topologies with reduced sensitivity to process mismatch. Such storage elements have lower minimum retention voltage that enables lower standby voltage and therefore lower standby leakage and standby power.... Agent: Wagner, Murabito & Hao LLP

20070013426 - Set/reset latch with minimum single event upset: A method and latch circuits are provided for implementing enhanced noise immunity performance. Each latch circuit includes an L1 latch and an L2 latch coupled to the L1 latch. Data is first latched in the L1 latch during a first half clock cycle and then latched in the L2 latch... Agent: Ibm Corporation RochesterIPLaw Dept 917

20070013427 - Delay circuit: A delay circuit has a second delay element 8 supplied with a delay time control signal Vcntl from a frequency variable oscillator 2 including a first delay element 8 of which delay time as a concomitant of signal propagation is controlled by a delay time control signal and a phase... Agent: Arent Fox PLLC

20070013428 - Differential clock tree in an integrated circuit: A clock distribution network having: a main trunk configured to provide a differential clock signal; a plurality of branches coupled to the main trunk for distributing the differential clock signal to a plurality of circuit elements on the integrated circuit; and a plurality of switches coupling the main trunk to... Agent: Xilinx, Inc Attn: Legal Department

20070013429 - Clamping circuit to counter parasitic coupling: A clamper circuit (1) receives an input signal (3) from the signal wire being clamped, i.e. the victim wire. The clamper circuit (1) also receives aggressor signals (5, 7) from aggressor wires, the aggressor wires being the signal wires that can potentially induce crosstalk on the victim wire. An output... Agent: Philips Intellectual Property & Standards

20070013430 - Ramp down method and apparatus for stabilizing charge on a floating gate: A method and apparatus for stabilizing the charge on a floating gate in a floating gate reference voltage generator. After an initial high voltage set mode, the method and apparatus allows for a controlled ramp down sequence to ramp down the voltages at the floating gate erase and program electrode... Agent: Nixon Peabody, LLP

20070013431 - Tunnel device level shift circuit: A floating gate circuit having a floating gate and a level shift circuit. A first tunneling device formed between a first and second tunnel electrode is included for removing electrons from the floating gate. Electrons are injected onto the floating gate without the use of a tunneling device, e.g., using... Agent: Nixon Peabody, LLP

20070013432 - Semiconductor device and method of controlling the same: A semiconductor device includes: a transmission switch having multiple first FETs connected in series between a first terminal connected to a transmission part and a second terminal connected to a common connection portion, gates of the multiple first FETs being connected to transmission drive circuits; a reception switch having multiple... Agent: Westerman, Hattori, Daniels & Adrian, LLP

20070013433 - Temperature compensation for internal inductor resistance: An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programable attenuation and a programable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers... Agent: Sterne, Kessler, Goldstein & Fox PLLC

20070013435 - Charge pump circuit: A charge pump circuit comprises a decoder for generating a plurality of control signals, a ring oscillator an output frequency of which varies according to the plurality of the control signals, a charge pump for generating a high voltage, which is higher than an external voltage, according to an output... Agent: Marshall, Gerstein & Borun LLP

20070013434 - Voltage regulated charge pump with regulated charge current into the flying capacitor: A charge pump circuit with a regulated charge current where the amount of current flowing into the flying capacitor depends on the magnitude of the output voltage error, using an OTA to convert the output voltage error into a current. Thus the flying capacitor is not charged when the output... Agent: George O. Saile

20070013436 - Bandgap reference circuit: The present invention provides a bandgap reference circuit, which includes a first current source, a second current source, a first reference circuit, a second reference circuit, and a selection circuit. The first reference circuit is coupled to the first current source and the second current source for outputting a first... Agent: J C Patents, Inc.

20070013437 - Leakage current compensated system: A leakage current compensated multiplex driver system includes a multichannel mux having a predetermined leakage current at the switched side of each channel and a leakage current compensation circuit associated with the switched side of each channel for providing a compensation current matched to the predetermined leakage current.... Agent: Iandiorio & Teska

20070008015 - High speed ramp generator: A high speed ramp generator is presented. The high speed ramp generator is advantageous over the prior art because it provides a ramp response without the delay incident with a simple integrator approach. A closed loop system generates a continuous ramp and, in an open loop manner, subtracts a mirror... Agent: The Hecker Law Group

20070008016 - Slicer with large input common mode range: A slicer with large input common mode range is provided. The slicer includes an input stage coupled to receive an input signal, a current source for providing current for the input stage, a self-biased load coupled to the input stage to provide an initial output signal, and an inverter for... Agent: Squire, Sanders & Dempsey L.L.P.

20070008017 - System and method for controlling input buffer biasing current: A system and method for controlling input buffer biasing current include an input buffer circuit with an input current detector circuit configured to generate a plurality of discrete biasing control signals. At least one input buffer is configured to adjust the biasing current in response to the plurality of discrete... Agent: Trask Britt

20070008018 - Waveform generating circuit and spread spectrum clock generator: A spread spectrum clock generator is provided which improves the spread spectrum effect with little increasing the circuit cost by modifying the shape of a triangular wave used for frequency modulation by as simple method. The output signal of the modulation waveform generating circuit has such a modulation waveform as... Agent: Finnegan, Henderson, Farabow, Garrett & Dunner LLP

20070008019 - Mechanical control elements for organic polymer electronic devices: A switching element for polymer electronic devices is constructed from organic materials.... Agent: Carella, Byrne, Bain, Gilfillan, Cecchi, Stewart & Olstein

20070008020 - Output buffer circuit: The present invention relates to an output buffer circuit. The output buffer circuit includes an input stage of which one end receives an input voltage and the other end receives an output voltage; a class AB output stage that increases a current flowing in the output stage when the difference... Agent: Lowe Hauptman Berner, LLP

20070008021 - Elastic pipeline latch with a safe mode: An elastic pipelined latch. The latch includes a control input for configuring the latch into a repeater state or a latch state, a drive component responsive to the control input and for driving an input signal through as an output signal, and a pulse width/inhibit component coupled to the drive... Agent: Wagner, Murabito & Hao LLP Third Floor

20070008022 - Delay circuit: The present invention provides a delay circuit in which normal CMOS type inverters and modified inverters added with delay PMOSs on the power supply voltage VDD terminal side are alternately cascade-connected. A correction circuit that supplies a control signal to the gates of the delay PMOSs is provided in association... Agent: Nixon Peabody, LLP

20070008023 - Differential-type delay cell circuit: A differential-type delay cell is disclosed herein. The delay cell provides two signal paths, each of which has a capacitor connected to the ground. The capacitance difference between the two capacitors determines the finest delay resolution of the delay cell. The delay cell does not rely on logic gates to... Agent: Rabin & Berdo, PC

20070008024 - Gate clock circuit and related method: A gate clock circuit and related method for generating a gate clock signal according to a clock and an enable signal. The gate clock circuit includes a transmission unit for receiving an enable signal and a clock signal, a latch unit connected to the transmission unit for generating a latch... Agent: North America Intellectual Property Corporation

20070008025 - Gate clock circuit and related method: A gate clock circuit and related method for generating a gate clock signal according to a clock and an enable signal. The gate clock circuit includes a transmission unit for receiving an enable signal and a clock signal, a latch unit connected to the transmission unit for generating a latch... Agent: North America Intellectual Property Corporation

20070008026 - Clamping circuit: A clamping circuit for restoring the DC level of video input signals. The clamping circuit comprises a coupling capacitor, a latch, a logic element, a charge switch, and a constant current source. The latch is coupled to the coupling capacitor to receive a video input signal therethrough and comprises a... Agent: Thomas, Kayden, Horstemeyer & Risley, LLP

20070008027 - Semiconductor devices: A CMOS circuit in low-voltage implementation, low power-consumption implementation, high-speed implementation, or small-size implementation. In a circuit which uses a FD-SOI MOST where a back gate is controlled by a well, voltage amplitude at the well is made larger than input-voltage amplitude at the gate. Alternatively, the circuit is modified... Agent: Stanley P. Fisher Reed Smith Hazel & Thomas LLP

20070008028 - Over boosting prevention circuit: In a over boosting prevention circuit that prevents over boosting of a voltage boosting circuit, ripples caused in the voltage boosting circuit are removed to prevent malfunctioning. The over boosting prevention circuit controls the output voltage Vout (<0V) of a charge pump circuit so that a difference (Vdd−Vout) between the... Agent: Morrison & Foerster LLP

20070008029 - Semiconductor device containing charge pump type step-up circuit featuring bipolar transistor for carrying out initial charging: A semiconductor device includes a first conductivity type semiconductor substrate, and a charge pump type step-up circuit formed in the semiconductor substrate. The step-up circuit includes a charge pump circuit and a bipolar transistor. The charge pump circuit has an input line to which a power supply voltage is to... Agent: Young & Thompson

20070008030 - Control system for programmable filters: Control system for programmable filters, master-slave calibration system and fully programmable high precision filter for use in such control system, such filters being provided with a filter input and a filter output including a first, first order low pass filter section comprising first and second mutually identical operational transconductance amplifiers... Agent: Robert M. Mcdermott, Esq.

20070001713 - Phase detecting circuit having adjustable gain curve and method thereof: A phase detecting circuit having an adjustable gain curve includes a plurality of phase detectors and a logic circuit The phase detectors detect phase differences between a data signal and a plurality of clock signals by comparison to output a plurality of control signals. The clock signals have the same... Agent: Birch Stewart Kolasch & Birch

20070001714 - Low-power supply voltage level detection circuit and method: An input power supply voltage level detection circuit and method are presented. The circuit includes a main detector core and a two-inverter buffer block that can include a first inverter and a second inverter. The circuit receives a voltage input signal and outputs a voltage output signal that is substantially... Agent: Sterne, Kessler, Goldstein & Fox PLLC

20070001715 - Power supply output voltage trimming: A power supply trim control signal is produced by integrating differences between monitored and target values of the output voltage of a power supply. Register storage requirements are reduced by producing the target value from a nominal voltage value and one of a plurality of margin offsets selected in accordance... Agent: Smart & Biggar P.o. Box 2999, Station D

20070001717 - Driver circuit: A driver circuit for outputting an output signal corresponding to an input signal given to the driver circuit, includes a voltage generating unit for outputting a basic output voltage corresponding to the input signal, a first buffer circuit for outputting an output voltage corresponding to the basic output voltage outputted... Agent: Osha Liang L.L.P.

20070001716 - High speed output buffer with ac-coupled level shift and dc level detection and correction: A high speed output buffer including an input circuit providing first and second signals within a first voltage range having a first common mode voltage, an AC interface receiving the first and second signals and providing first and second preliminary drive signals, a detection and correction circuit that corrects a... Agent: The Law Offices Of Gary R. Stanford

20070001718 - Phase adjustment for a divider circuit: A divider circuit receives an input signal and at least one phase adjustment control signal and supplies a phase adjustable output signal. The divider circuit includes a state machine providing N states, with no phase adjustment, to provide as the output signal the input signal divided by N. Each state... Agent: Zagorin O'brien Graham LLP

20070001719 - Tunable high-speed frequency divider: A locking range of a current mode logic (CML) frequency divider circuit is tunable by dynamically adjusting a tail current of the frequency divider circuit according to a control signal. The control signal may be based on at least one control signal coupled to tune a controllable oscillator. The control... Agent: Zagorin O'brien Graham LLP

20070001721 - Power-on reset circuit: A power-on reset circuit has a reset starting circuit, a reset finishing circuit, and a latch circuit. The reset starting circuit generates a reset starting signal in response to a power voltage. When the power voltage reaches a predetermined reset finishing voltage, the reset finishing circuit generates a reset finishing... Agent: North America Intellectual Property Corporation

20070001720 - System and method for monitoring a power supply level: A system and method are provided herein for monitoring the integrity of a power supply by monitoring a level of the power supply voltage supplied to one or more system components. The method, as described herein, includes setting a bit in a status register after the power supply level reaches... Agent: Daffer Mcdaneil LLP

20070001723 - Clock and data recovery circuit and method thereof: A clock and data recovery circuit having parallel dual path is disclosed, which includes a phase detecting circuit, a first charge pump, a proportional load circuit, a second charge pump, an integration load circuit, and a voltage control oscillating circuit. The phase detecting circuit respectively compares a phase difference between... Agent: Birch Stewart Kolasch & Birch

20070001722 - Recovery of client clock without jitter: The present invention provides a system, apparatus and method for recovering a client signal clock. The present invention is able to more effectively remove jitter within a clock signal by providing a phase shifting element in the feedback of a PLL system to compensate for sudden changes in an input... Agent: Infinera Corporation

20070001724 - Delay locked loop circuit: A delay locked loop circuit is disclosed. The circuit comprises a clock receiver for outputting an external clock, an inverted clock, which is an inverted version of the external clock, and a reference clock, a multiplexer for receiving the external clock and the inverted clock and selectively outputting any one... Agent: Marshall, Gerstein & Borun LLP

20070001725 - Apparatus and a method to provide time-based edge-rate compensation: A method and an apparatus to provide time-based edge-rate compensation have been disclosed. In one embodiment, the apparatus includes a reference pad, a reference circuit coupled to the reference pad, the reference circuit being operable to charge and to discharge a reference voltage at the reference pad, and an edge-rate... Agent: Blakely Sokoloff Taylor & Zafman

20070001726 - Duty cycle correction device: Disclosed is a duty cycle correction device for correcting a duty cycle of a clock signal output from a delay locked loop (DLL) device by using a phase mixer. The duty cycle correction device comprises: a mixer for receiving a first clock signal and a second clock signal and outputting... Agent: Ladas & Parry LLP

20070001729 - Digital storage element architecture comprising dual scan clocks and preset functionality: A digital storage element comprising a master transparent latch that receives functional data from a data input port and scan data from a scan input port and comprises a master feedback loop with a first transistor coupled to the master feedback loop. The first transistor also is coupled to electrical... Agent: Texas Instruments Incorporated

20070001728 - Digital storage element architecture comprising dual scan clocks and reset functionality: A digital storage element comprising a master transparent latch that receives functional data from a data input port and scan data from a scan input port and comprises a master feedback loop with a first transistor coupled to the master feedback loop. The first transistor also is coupled to a... Agent: Texas Instruments Incorporated

20070001727 - Static latch: A static latch (80) transfers input data (D) and its complement (DN) to an output terminal (100) and a complementary output terminal (98) when enabled and maintains the input data (D, DN) on the output terminals (100,98) when not enabled. The input data (D, DN) gate second and third transistors... Agent: Philips Intellectual Property & Standards

20070001733 - Digital storage element architecture comprising integrated 2-to-1 multiplexer functionality: A digital storage element comprises a master transparent latch that receives functional data signals from data input ports and scan data signals from a scan input port. The data input ports are coupled to a two-input, one-output multiplexer adapted to receive the functional data signals and to selectively output one... Agent: Texas Instruments Incorporated

20070001730 - Digital storage element architecture comprising integrated 4-to-1 multiplexer functionality: A digital storage element comprises a master transparent latch that receives functional data signals from data input ports and scan data signals from a scan input port, the data input ports coupled to a four-input, one-output multiplexer adapted to receive the functional data signals and to selectively output one of... Agent: Texas Instruments Incorporated

20070001731 - Digital storage element architecture comprising integrated multiplexer and reset functionality: A digital storage element comprises a master transparent latch that receives functional data signals from data input ports and scan data signals from a scan input port, the data input ports coupled to a four-input, one-output multiplexer that receives the functional data signals and selectively outputs one of the functional... Agent: Texas Instruments Incorporated

20070001732 - Digital storage element with dual behavior: A digital storage element comprises a master transparent latch that receives functional data from a data input port and scan data from a scan input port and a slave transparent latch coupled to the master transparent latch. The slave transparent latch comprises dedicated functional data and scan data output ports.... Agent: Texas Instruments Incorporated

20070001735 - Power output stage: A class D power output stage for switching a supply voltage comprises a limiting transistor with a controllable path and a control terminal, a complementary limiting transistor with a controllable path and a control terminal, a switching transistor with a controllable path and a control terminal, and a complementary switching... Agent: Jenkins, Wilson, Taylor & Hunt, P. A.

20070001734 - Semiconductor integrated circuit device: A low power consumption in a semiconductor integrated circuit device can be achieved by reducing a glitch power in a flip-flop. In a pulse-generator-incorporated auto-clock-gating flip-flop in which data latch is performed by using a pulsed clock, input data is latched based on an output of a dynamic XOR circuit,... Agent: Miles & Stockbridge PC

20070001737 - System and method of generating a clock cycle having an asymmetric duty cycle: A system and method are provided for producing two asymmetric duty cycle clock phases as outputs, where the duration of the active phase may be varied to generate clock signal having an asymmetric duty cycle. A circuit configured according to the invention includes a monostable clock generator configured to produce... Agent: Stevens Law Group

20070001736 - Variable-gain-amplifier based limiter to remove amplitude modulation from a vco output: An apparatus and method for generating high-speed clock signals using a voltage-controlled-oscillator (VCO) device. The apparatus implements a linear variable gain amplifier rather than a non-linear hard limiter to remove unwanted signal modulation in VCO output signals. Implementation of the linear variable gain amplifier leads to the generation of amplitude... Agent: Scully Scott Murphy & Presser, PC

20070001738 - Variable resistance circuit: A variable resistance circuit includes a PIN diode circuit which adjusts an RF resistance for PIN diodes according to a control voltage, a first means which level-shifts one control voltage by a level shift circuit and applies a non-linear characteristic to the so level-shifted control voltage using a zener diode... Agent: Trexler, Bushnell, Giangiorgi, Blackstone & Marr, Ltd.

20070001740 - Level shifter circuit: A level shifter circuit includes a level shifter unit and a latch unit. The level shifter unit receives two complementary input signals and converts the voltage levels of two complementary input signals. The latch unit latches the state of two output nodes before the low voltage supply is turned off.... Agent: Birch Stewart Kolasch & Birch

20070001739 - System and method automatically selecting intermediate power supply voltages for intermediate level shifters: The present invention provides for a system comprising a level shifter configured to receive a first clock signal from a first power domain, to receive a counter signal, to select one of a plurality of intermediate voltages in response to the received counter signal, and to generate a second clock... Agent: Ibm Corporation (cs) C/o Carr LLP

20070001741 - Interpolation: A steering current generator for a phase interpolator has a multiplicity of fine phase adjustment current sources, each of which is switchable to direct its current to one or other of two summing nodes. The current of each of those two summing nodes is supplemented by respective fixed always-on current... Agent: Texas Instruments Incorporated

20070001742 - Driving circuit for switching elements: A level shifting circuit, satisfying a requirement of a high tolerated dV/dt level, and a highly reliable inverter circuit, wherein a set pulse signal and a reset pulse signal, both of which are level-shifted to a potential side taking as reference a reference potential of a gate control terminal of... Agent: Antonelli, Terry, Stout & Kraus, LLP

20070001743 - Utilization of device types having different threshold voltages: A technique implements high impedance nodes using high threshold voltage devices that may generate less leakage current and may have a higher gate oxide breakdown voltage than standard devices in a particular manufacturing technology. Under at least one operating condition, for a particular power supply voltage, a circuit may unable... Agent: Zagorin O'brien Graham LLP

20070001744 - Switched current temperature sensing circuit and method to correct errors due to beta and series resistance: t

20070001745 - Charge pump for generating arbitrary voltage levels: A charge pump for generating an arbitrary voltage level includes “M” pieces of pump units PUi and “M+1” pieces of first switches Sj. The pump unit PUi includes a first terminal Ni,1 coupled to a reference voltage Vi,1, a second terminal Ni,2 coupled to a reference voltage Vi,2, a third... Agent: Jianq Chyun Intellectual Property Office

20070001746 - Selectably boosted control signal based on supply voltage: A technique implements high impedance nodes using high threshold voltage devices that may generate less leakage current and may have a higher gate oxide breakdown voltage than standard devices in a particular manufacturing technology. Under at least one operating condition, for a particular power supply voltage, a circuit may unable... Agent: Zagorin O'brien Graham LLP

20070001747 - Rapid supply voltage ramp: In one embodiment, an apparatus is provided for a system including an integrated circuit coupled to a node to receive a supply voltage and having bypass capacitors coupled in parallel with the integrated circuit to the node. The apparatus comprises a first capacitor, a switch coupled to the first capacitor,... Agent: Meyertons, Hood, Kivlin, Kowert & Goetzel, P.C.

20070001748 - Low voltage bandgap voltage reference circuit: A bandgap reference voltage generating circuit includes a proportional to absolute temperature (PTAT) voltage generating means generating a PTAT voltage. A complementary to absolute temperature (CTAT) voltage generating means generates a CTAT voltage. A temperature coefficient determining means interconnects the PTAT voltage generating means and the CTAT voltage generating means.... Agent: Hiscock & Barclay, LLP

20070001749 - Dual loop voltage regulation circuit of power supply chip: A dual loop voltage regulation circuit of power supply chip is provided, comprising a capacitor for providing a voltage signal, a comparator for comparing a first reference voltage signal and the voltage signal to output forward or backward trigger signal, a first switch triggered by a forward trigger signal, a... Agent: Harness, Dickey & Pierce, P.L.C

20070001750 - Reference voltage generating circuit: A reference voltage generating circuit for outputting a reference voltage having a level varying depending on the operation mode of a semiconductor device is disclosed. The reference voltage generating circuit includes a first reference voltage generator that outputs first and second initial reference voltages having different levels, a second reference... Agent: Marshall, Gerstein & Borun LLP

20070001752 - Internal voltage generation circuit of a semiconductor device: An internal voltage generation circuit of a semiconductor device is disclosed. The internal voltage generation circuit comprises a reference voltage generator for generating a reference voltage having different levels depending on different operation modes of the semiconductor device, an active voltage generator for generating an active internal voltage of a... Agent: Marshall, Gerstein & Borun LLP

20070001753 - Internal voltage generation circuit of semiconductor device: An internal voltage generation circuit of a semiconductor device includes: a comparator for comparing a reference voltage level with a detection voltage level to provide a comparison signal; an internal voltage output device for raising a voltage of an internal voltage output terminal to a predetermined level in response to... Agent: Blakely Sokoloff Taylor & Zafman

20070001751 - System and method for providing an accurate reference bias current: A system and related method are provided for producing a reference bias current that varies within a limited threshold from its nominal value based on band gap voltage, and that generates the bias current substantially independent from process and temperature. In one embodiment, the invention provides a process dependant voltage... Agent: Stevens Law Group

20070001754 - Discrete time filter having gain for digital sampling receivers: A discrete time filter achieves gain by sampling a signal using capacitors arranged in a one configuration and then changing the capacitors to a series configuration to develop a filter output voltage. In at least one embodiment, a variable gain filter is achieved by varying the number of capacitors that... Agent: The Law Offices Of John C. Scott, LLC C/o Intellevele

20070001755 - Switchable high-pass configuration and an optical receiver with a switchable high-pass configuration: The invention relates to a switchable high-pass filter arrangement which has a lower limiting frequency determining the high-pass filter behavior. The arrangement includes a transistor circuit, which has at least one transistor in a common-gate or common-base connection; a capacitive component in series with the input of the transistor circuit;... Agent: Eschweiler & Associates, LLC National City Bank Building