Miscellaneous active electrical nonlinear devices, circuits, and systems inventions 08/06

20060192592 - Circuit arrangement and method for data transmission: With the circuit arrangement and the associated method a start or announcement signal indicating a data transmission is sampled with a module-specific clock and on detection of the beginning of a start signal sent along with the payload data to be transmitted, the payload data to be transmitted is forwarded...

20060192593 - Method and apparatus for continuous-averaging counter-based digital frequency lock detector: Methods and apparatus are provided for counter-based digital frequency lock detection. A counter-based digital frequency lock detector in accordance with the present invention comprises a reference counter clocked by a reference clock and a target counter clocked by a target clock. The target counter is n bits and n is...

20060192594 - Linear phase detector with multiplexed latches: Linear phase detectors comprising circuits (1,2) receiving first and second clock signals (CLKOO, CLK90) for generating first and second control signals (UP,DOWN) for use in clock extractors and data regenerators have large delays due to long path lengths and many operations between input and output (insight). They can be made...

20060192595 - Sense amplifier: A sense amplifier includes at least two field effect transistors of identical conductivity type, each including a gate terminal, a source terminal, a drain terminal and a bulk terminal. The two field effect transistors are connected such that they are coupled back-to-back between a bit line and a reference line....

20060192596 - Integrated circuit having a low power mode and method therefor: An integrated circuit (70) includes a first power supply bus (72) and a second power supply bus (74). The first power supply bus (72) provides a first power supply voltage (VDD) to a first plurality of circuit elements (12 and 76). The second power supply bus (74) provides a second...

20060192597 - Temperature sensing circuits, and temperature detection circuits including same: Temperature sensing circuits are disclosed. One embodiment of a temperature sensing circuit includes a voltage divider and an analog multiplexer. The voltage divider network divides an analog voltage into multiple derived analog voltages. The analog multiplexer receives at least two of the derived analog voltages and a control signal, and...

20060192598 - Technique for expanding an input signal: A technique for expanding an input signal includes receiving the input signal at a first node of a voltage expander and generating a plurality of expanded signals on different outputs of the voltage expander responsive to the input signal. In certain embodiments, each of the expanded signals has a different...

20060192599 - Drive circuit for a firing element of an occupant protection system: A drive circuit for a firing element of an occupant protection system comprises first and second supply potential terminals and first and second firing element terminals. A first semiconductor switching element is integrated in a first semiconductor body and has a first load terminal coupled to the first supply potential...

20060192600 - Synchronous output buffer, synchronous memory device and method of testing access time: An output buffer includes an output terminal, a pull up module, a pull down module and an output latching module. The pull up module pulls up the output terminal to a first source voltage when the pull up module is active. The pull down module pulls down the output terminal...

20060192601 - Method and apparatus for digital phase generation at high frequencies: An apparatus and method for generating phase related clocks, includes delaying a clock input by a cycle delay magnitude to generate a cycle delay signal and N delay taps is disclosed. Each delay tap has a delay equal to a fractional amount of the cycle delay magnitude. The method further...

20060192602 - Delay locked loop circuit in semiconductor device and its control method: A delay locked loop (DLL) device includes a first and a second input buffers for receiving an external clock, a multiplexer for selectively outputting a first and a second internal clocks based on a most significant bit (MSB) signal, a delay means for delaying the first and the second internal...

20060192603 - Wave shaping output driver to adjust slew rate and/or pre-emphasis of an output signal: Integrated circuit, system, method and machine readable media embodiments adjust a slew rate and/or a transmit pre-emphasis of an output signal at selected phases during a bit time. A timing circuit provides a plurality of delayed data signals in response to a clock signal. A plurality of adjustable impedance circuits,...

20060192604 - Integrated circuit storage element having low power data retention and method therefor: A storage element (10) includes a first latch (12) and a second latch (14). The first latch (12) is coupled to a first power supply voltage terminal for receiving a first power supply voltage. The second latch (14) is coupled to a second power supply voltage terminal. The second power...

20060192605 - Amplitude setting circuit: An amplitude setting circuit for setting an amplitude level of its output signal corresponding to an input signal. By setting a current flowing through a first diode-connected transistor (Q5) and a current flowing through a first drive transistor (Q1) to be in a predetermined relationship, variation with temperature in potential...

20060192606 - Forward biasing protection circuit: A forward biasing protection circuit is provided. More specifically, there is provided a device comprising a transistor, a resistive element coupled to the body terminal of the transistor, and a clamping element coupled in parallel to the resistive element and configured to limit a voltage between the source terminal and...

20060192607 - Boost voltage generating circuit including additional pump circuit and boost voltage generating method thereof: A boost voltage generating circuit of a semiconductor device includes a main pump circuit having a transfer transistor, the main pump circuit to boost a voltage of a boost node and to transfer charge from the boost node to an output node through the transfer transistor in response to at...

20060192608 - Reference-voltage generating circuit: A disclosed reference-voltage generating circuit includes a supply voltage adjusting circuit for adjusting an external supply voltage Vcc and outputting predetermined constant voltages VA and VB; a first voltage supply circuit for generating a voltage Vpn that has a negative temperature coefficient by using the voltage VA; and a second...

20060192610 - Power supply voltage step-down circuit, delay circuit, and semiconductor device having the delay circuit: A delay circuit has a circuit structure dominated by an NMOS or a PMOS transistor. The delay circuit is supplied with, as a power supply voltage, an output voltage of a power supply voltage step-down circuit having a level generating circuit for generating a reference voltage obtained by an offset...

20060192609 - Reference voltage generating circuit with ultra-low power consumption: A reference voltage generating circuit with ultra-low power consumption, which includes: a constant current circuit part generating a first constant current from a supply voltage; a current mirror circuit part mirroring the constant current and supplying a second constant current; a voltage control circuit part receiving the second constant current...

20060192611 - Body-biased enhanced precision current mirror: A body-biased enhanced current mirror reference circuit is disclosed wherein the body bias voltage of a current mirror device is varied to adjust its threshold voltage. Both the drain and body potentials of a replica mirror transistor are controlled to selected values. The drain is set to an expected DC...

20060192612 - Capacitor reliability for multiple-voltage power supply systems: A capacitor circuit having improved reliability includes at least first and second capacitors, a first terminal of the first capacitor connecting to a first source providing a first voltage, a first terminal of the second capacitor connecting to a second source providing a second voltage, the first voltage being greater...

20060192613 - Gm-c time constant tuning circuit: A circuit including a Gm-C filter and an automatic Gm-C time constant tuning circuit is provided. The tuning circuit includes a reference conductor, a reference capacitor coupled to the reference conductor, a comparator generating signals according to a reference signal and the voltage signal at the output of the reference...

20060192614 - Gigabit ethernet transceiver with analog front end: Circuitry to remove switches from signal paths in integrated circuit programmable gain attenuators. Programmable gain attenuators and programmable gain amplifiers commonly switch between signal levels using semi-conductor switches. Such switches may introduce non-linearities in the signal. By isolating the switches from the signal path linearity of the PGA can be...

20060186926 - Dual-purpose uplinks used in a fault-tolerant stack: A fault-tolerant stack of low cost switches each having only two dual-purpose uplinks is enabled by utilizing a specified topology for connecting the uplinks and implementing a recovery algorithm on each switch....

20060186927 - Method and circuit for filtering glitches: A circuit for filtering glitches that corrupt a digital input signal includes an enable path input with the digital signal and a reset signal. The enable path generates a corresponding active output signal when the reset signal is null and the digital signal assumes a logic active value, or a...

20060186928 - Comparators capable of output offset calibration: Comparators outputting offset calibration. A MOS current mode logic (MCML) circuit receives input signals and generates differential logic signals on output terminals thereof, and comprises a calibration unit coupled to the output terminals, calibrating output offsets at the output terminals according to digital calibration codes. An output stage is coupled...

20060186929 - Chip for operating in multi power conditions and system having the same: An apparatus for controlling an I/O interface of a chip operated in multi-power conditions includes an enable signal generator for generating an enable signal based on a chip power down signal; a reference voltage generator for generating a predetermined reference voltage in response to the enable signal; a comparator for...

20060186930 - Direct digital frequency synthesizer: A frequency synthesiser according to the direct digital synthesis method is provided. The frequency synthesiser includes a phase accumulator for the cyclical incrementation of a phase signal by a phase increment M present at the input of the phase accumulator, a memory unit with a table of sine-function values stored...

20060186931 - Method for locking a synthesised output signal of a synthesised waveform synthesiser in a phase relationship with an input signal, and a digital waveform synthesiser for producing a synthesised output signal in a phase relationship with an input signal: A digital waveform synthesiser (1) is implemented as a single chip integrated circuit on a single chip (2) and comprises a direct digital synthesiser (10) which produces a synthesised output signal waveform on an output terminal (4) which is substantially phase and frequency locked to the phase and frequency of...

20060186932 - Analog buffers composed of thin film transistors: Analog buffers with a precise gate to source voltage compensation and a small DC offset, by storing an input offset voltage to be used as an output offset voltage to reverse the offset in the input. A first source follower at the input end and a second source follower at...

20060186934 - Driver circuit: A driver circuit includes a differential amplifier for receiving an input signal, and first and second transistors of different conductivity types. The first and second transistors are connected serially between two power supply terminals in a form (source follower) in which the sources of the transistors are connected to an...

20060186933 - Gate driving circuit: A gate driving circuit has a variable current carrying path that switches a current carrying path among a driving target device, a DC power source and a reactor to operate in plural operation modes including at least a hold mode, a preparation mode, and an execution mode. The variable current...

20060186935 - Circuit and method for generating boost element drive signals for semiconductor memory devices with mode register set signals: Disclosed herein is a circuit and method for generating a boost element drive signal in a semiconductor memory device with a mode register set signal. The boost element drive signal generation circuit includes a preliminary drive signal generation unit and a level shifter. The preliminary drive signal generation unit generates...

20060186936 - Delay circuitry and method therefor: One use for delay adjustment circuit (32), coarse-grain delay offset circuit (34), and fine-grain delay synthesis circuit (36) may be as part of a delay replication circuit (30) used to replicate the frequency versus voltage behavior of an integrated circuit (29). Also, a circuit (30) and method for determining optimal...

20060186937 - Active noise regulator: The invention proposes noise suppression circuits mounted on the package of a high power, high frequency ULSI component. In this architecture, termed an active noise regulator (ANR), charge is stored on dedicated reservoir capacitors at a voltage substantially higher than the operating voltage of the ULSI device. These reservoir capacitors...

20060186938 - Circuit and method for determining optimal power and frequency metrics of an integrated circuit: One use for delay adjustment circuit (32), coarse-grain delay offset circuit (34), and fine-grain delay synthesis circuit (36) may be as part of a delay replication circuit (30) used to replicate the frequency versus voltage behavior of an integrated circuit (29). Also, a circuit (30) and method for determining optimal...

20060186939 - Clock adjusting method and electronic device with clock adjusting function: A method for adjusting a clock and an electronic device with clock adjusting function are provided. In the method of adjusting the clock, the electronics device is driven with a first clock when the electronic device is during the reset-inactive state. Then, the electronic device is driven with a second...

20060186940 - Multi-phase clock generator and generating method for network controller: The present invention discloses a multi-phase clock generator of a network controller for generating a set of multi-phase clocks, and a method thereof. The multi-phase clock generator includes a first gating element and a second gating element. The first gating element operates according to a first control clock and generates...

20060186941 - Minimum norm sence reconstruction for optimal spatial response: A novel magnetic resonance imaging method is described, wherein undersampled magnetic resonance signals are acquired by a receiver antenna system having spatial sensitivity profiles and the image being reconstructed from the undersampled magnetic resonance signals and the spatial sensitivity profiles. The reconstruction of the image is provided by an optimization...

20060186942 - Level shifter circuit and semiconductor memory device using same: A level shifter circuit comprises a first output MIS transistor of a first conductivity, and a second output MIS transistor of a second conductivity type having a second threshold voltage. The former has a first threshold voltage, wherein the output voltage is positively fed back to a gate terminal and...

20060186943 - Ultra-low-power voltage transform circuit: A voltage transform circuit transforms a transferred voltage to a desired magnitude of voltage. The voltage transform circuit includes: a first power supply unit for providing a digital voltage (Vdd-1) of a first magnitude; a second power supply unit for providing an analog voltage (Vaa-2) of a second magnitude; and...

20060186944 - Process independent voltage controlled logarithmic attenuator having a low distortion and method therefor: A process independent voltage controlled logarithmic attenuator has an attenuator control stage block having a first input coupled to a controlled input and a second input coupled to an offset generator. An attenuator transistor is coupled to the attenuator controlled stage block. An output of the attenuator controlled stage block...

20060186945 - Circuit apparatus and method for operating the same: An LSI includes an operational unit and a switching circuit, and an LSI includes an operational unit and a switching circuit. The operational unit of the LSI generates a switching control signal based on a switching table for supply to the switching circuit. In the switching circuit, each of terminals...

20060186946 - Detecting excess current leakage of a cmos device: A system (10,90), apparatus (12,30,40,50,60,70) and method (100) is disclosed for detecting excess current leakage between drain/source of a metal oxide semiconductor (MOS) transistor (36,46) within a complementary MOS (CMOS) environment. A load control (32,42) is arranged as a compliment to the MOS transistor. A comparator (34,44) is electrically connected...

20060186949 - Charge-coupled device: A CCD shift register capable of switching between two-phase driving and three-phase driving in which crosstalk among clock signal lines is reduced and a decrease in transfer efficiency is prevented. Transfer electrodes disposed at regular intervals along a channel region are supplied with clock signals through clock signal lines. Three...

20060186947 - Multi-stage charge pump without threshold drop with frequency modulation between embedded mode operations: A multimode charge pump circuit has a single charge pump that is responsive to a set of clock signals. The set of clock signals is provided in a first mode with a variable frequency according to a first function of the supply potential and temperature, and in a second mode...

20060186948 - Programmable clock booster system: A programmable clock booster system including a clock booster circuit including at least one boost capacitor connected between a first node and a second node for sampling an input voltage in a first phase and applying a boosting voltage to said second node during a second phase, and a programmable...

20060186950 - Low supply voltage bias circuit, semiconductor device, wafer and system including same, and method of generating a bias reference: A bias generator and a method of generating a bias reference are disclosed. A reference transistor is connected in a diode configuration. An n-channel transistor connects in series with the reference transistor. A resulting reference current through the two transistors is controlled by the gate voltage on the n-channel transistor....

20060186951 - Low noise lowpass filter: A differential biquad filter includes positive and negative single ended circuits connected between first and second power supply terminals. Each single ended circuit includes a single input terminal; a transistor having a control terminal, and first and second main terminals; a single output terminal corresponding to the control terminal of...

20060186952 - Programmable/tunable active rc filter: A programmable/tunable active low-pass filter at least has the resistors, capacitors and shunt control means. It uses the resistor ladder that is structured with various fixed resistors to implement the shunt control means. The cut-off frequency of a filter is associated with the time constant, which is determined by equivalent...

20060181314 - Comparator with hysteresis: In one embodiment, a comparator is provided with a first differential input stage that receives an input voltage and a reference voltage and produces a first differential output, and a second differential input stage that has differential inputs and produces a second differential output. A comparator stage produces a comparator...

20060181315 - Bus holders having wide input and output voltage ranges and tolerant input/output buffers using the same: A bus holder includes a first inverter, a second inverter and a pass switch. The first inverter is coupled between a first power supply voltage node and a second power supply voltage node, and receives an input signal via an input terminal to output a first output signal having an...

20060181316 - Self-initializing frequency divider: A frequency divider apparatus is a closed loop system of a recirculating memory element, at least one feedback memory element and an end memory element in series combination. Each memory element accepts a common clock. An end memory element output is logically combined with at least one of the other...

20060181317 - Resistive memory device having resistor part for controlling switching window: A resistive memory device having a resistor part for controlling a switching window. The resistive memory device of this disclosure can control a switching window to assure operational reliability thereof. In addition, since the memory device is realized by additionally providing only the resistor part for controlling a switching window...

20060181318 - Radio transceiver having a phase-locked loop circuit: The invention relates to a phase-locked loop circuit (1) in a radio transceiver for the detection of the linear operation of a first voltage controlled oscillator (2), which comprises a frequency divider (8), a reference oscillator (10), a phase detector (12) to compare the phases of the reference oscillator (10)...

20060181319 - Phase adjustment method and circuit for dll-based serial data link transceivers: A delay locked loop circuit with a first flip flop driven by a 0° clock and receiving the input data. A second flip flop by a 180° clock and receiving the input data. A first demultiplexer receives an output of the first flip flop and outputs peak data. A second...

20060181320 - Circuit for optimizing the duty cycle of a received clock transmitted over a transmission line: Data signals are transmitted over transmission lines in groups to receivers in a receiving IC. Each group of data signals has a differential clock used in synchronizing and detecting the data signals. The data signal eye windows vary with timing jitter in the data signals relative to the clock edges...

20060181321 - Systems and methods for minimizing harmonic interference: Systems and methods are disclosed for minimizing nth-order harmonic associated with a square wave clock signal having a predetermined frequency and duty cycle. The system changes the duty cycle of the clock to eliminate or suppress the nth-order harmonic of the clock; and generates a low-interference clock having the changed...

20060181322 - Input circuits configured to operate using a range of supply voltages: An input circuit includes an input signal transmission circuit configured to output a first transmission signal at a first output node in response to an input signal at an input node, and a Schmitt trigger inverter configured to output a second transmission signal at a second output node in response...

20060181323 - System and method for balancing delay of signal communication paths through well voltage adjustment: A method of balancing signal interconnect path delays between an analog domain and a digital domain of an integrated circuit includes applying a test signal to a selected one of a plurality of communication paths between the analog domain and the digital domain. A rising edge delay and a falling...

20060181324 - Programmable delay element: Delay elements and delay lines having glitchless operation are disclosed. By way of example, apparatus for delaying an input signal comprises a reference current generator for generating a constant current, wherein the constant current is insensitive to a variation of a power supply voltage, at least one variable bias voltage...

20060181326 - System and method for local generation of a ratio clock: A system for locally generating a ratio clock from a global clock based on a global clock gate signal includes a staging unit, a pass gate, and a state machine. The state machine is electrically connected to an output of the staging unit and an input of the pass gate....

20060181325 - System and method for providing on-chip clock generation verification using an external clock: A system and method for performing functional verification of a device, and in particular a technique for performing phase-locked loop (PLL) functional verification by the device which contains the PLL circuitry. A relatively slow-speed external clock is provided to the device, and is used to generate control signals to a...

20060181327 - Operating current modifying device and method: An operating current modifying device is provided for a power generating element. The power generating element generates an output power when the operating current is larger than a threshold current in the power generating element. A functional relationship is between the threshold current and the temperature of the electrical device....

20060181328 - High-frequency switching device and semiconductor device: The first terminals of a plurality of resistor elements are connected to the intermediate connection points of a plurality of FETs connected in series, and a voltage, having a phase opposite to that of the voltage applied to the gate terminals of the plurality of FETs, is applied to the...

20060181329 - Circuit arrangement and transistor control method: In order to improve a circuit arrangement (100) and a method of controlling at least one transistor (10, 12, 14, 18), especially of controlling the resistance value of at least one MOS transistor with vanishing DC modulation in such a way that a compensation of resistance variations without control deviation...

20060181330 - Method and apparatus for protecting efuse information: A method and apparatus are provided for protecting electronic fuse (eFuse) information. A current balancing circuit is provided that maintains a constant current demand on the eFuse voltage supply that is sufficient to blow an eFuse. Normally the constant current is applied to a semiconductor core. When an eFuse is...

20060181331 - Trimming fuse circuit with latch: A trimming fuse circuit with a latch is disclosed. The trimming fuse circuit includes: a first CMOS transistor having a first PMOS and a second NMOS, wherein said first PMOS has a size smaller than that of said first NMOS; a second CMOS transistor having a second PMOS and a...

20060181332 - Voltage supply circuit including a iii-nitride based power semiconductor device: A voltage supply circuit for providing an output DC voltage from an input DC voltage bus that includes a III-nitride based power semiconductor device series connected between the input DC voltage bus and an output capacitor, which is switchable from an on state to an off state in order to...

20060181333 - Self regulating charge pump: A charge pump includes a transistor of the charge pump modified to regulate a supply voltage to substantially reduce noise from the supply voltage when charging the capacitor of the charge pump and subsequently reduces noise at the voltage output. The charge pump may have a regulating transistor for charging...

20060181334 - High voltage generator for use in semiconductor memory device: The present invention generates a boosted voltage by preventing a latch-up phenomenon during an initial operating time, i.e., when a power voltage is initially inputted. The present invention includes a level-detecting block for comparing an high voltage with a high reference voltage and for generating a level detect signal; an...

20060181336 - Bandgap reference voltage generator without start-up failure: Provided is a bandgap reference voltage generator without a start-up failure, including: a reference voltage generator, generating a bandgap reference voltage; a current provider providing a start-up current to the reference voltage generator using a predetermined power; and if the current provider fails to provide the start-up current to the...

20060181335 - Low voltage bandgap reference (bgr) circuit: A low voltage bandgap reference circuit based on a current summation technique where reference voltages with positive and negative temperature coefficients are generated by a first circuit. These reference voltages are coupled to amplifying circuits which generate reference voltages with equal and opposite temperature coefficients based on the ratio of...

20060181337 - Digitally tunable high-current current reference with high psrr: A digitally tunable low voltage CMOS current reference is disclosed. A tunable current reference circuit is provided that includes a current source circuit that is coupled to a power supply voltage. The current source circuit provides a stable current reference output regardless of fluctuations in the power supply voltage. Multiple...

20060181339 - Semiconductor device with resistor element: A semiconductor device includes first, second, third and fourth resistor elements. The first to fourth resistor elements have first ends commonly connected to a first node, and operate in one of first and second operation modes which are switchable. The first and second resistor elements have second ends connected to...

20060181338 - Stacked cmos current mirror using mosfets having different threshold voltages: A stacked CMOS current mirror using metal oxide semiconductor field effect transistors (MOSFETs) having different threshold voltages is disclosed. The stacked CMOS current mirror includes a first MOSFET having a source and a gate which are connected to a first input current terminal, a second MOSFET having a source connected...

20060176082 - Method and apparatus for detecting leading pulse edges: An apparatus and method for detecting leading pulse edges of a signal includes a controller, hysteresis threshold comparators and qualification timers. The controller uses the outputs from the timers in order to determine whether or not a transition of the input signal constitutes a leading pulse edge of the input...

20060176083 - Single ended three transistor quasi-static ram cell: A single ended three transistor quasi-static RAM cell comprises two cross coupled MOS transistors and one select MOS transistor connected to drain of one of the aforementioned MOS transistors wherein drains of both cross coupled MOS transistors are each connected to anode of one of two PN diodes functioning as...

20060176084 - Amplitude adjusting circuit: An amplitude adjusting circuit comprises a first current mirror where a variable current of a variable current source is copied into each of 1st-3rd transistors; a second current mirror where the variable current is copied into each of 11th-13th transistors; a third current mirror having 6th-7th transistors where a current...

20060176085 - Comparator circuit with reduced switching noise: A comparator circuit includes a differential amplifier circuit, a latch circuit, and a control signal generating circuit. The latch circuit includes a pair of cross-coupled inverting amplifiers that pull the output signals of the differential amplifier to the high and low logic levels, a control transistor that activates the latch...

20060176086 - Circuit for generating a floating reference voltage, in cmos technology: A circuit generates a reference voltage that is independent of temperature. The circuit is built on a substrate according to a CMOS technology, and includes a first stage for generating a first current proportional to temperature and a second stage for generating a second current inversely proportional to temperature. These...

20060176087 - Low noise output buffer capable of operating at high speeds: Output buffers which operate at high speeds require delicate handling of the noise on the supply lines. This necessitates control be exercised over current slew rate not only on the rising edge of current but also on the falling edge of the current. A circuit provides control over the current...

20060176088 - Semiconductor integrated circuit device: A semiconductor integrated circuit device with a power-on detecting circuit, wherein the power-on detecting circuit includes: first and second power supply terminals between which an external power supply voltage is to be supplied; a first diode circuit having a first resistor and a first diode connected in series between the...

20060176089 - Phase-locked loop circuit and data reproduction apparatus: This invention relates to a phase-locked loop circuit and a data reproduction apparatus, which can reduce a processing time that is required for initial adjustment in the data reproduction apparatus. In a digital data reproduction apparatus having two control functions, i.e., phase and duty adjustments for binarized data, the phase...

20060176091 - Delay locked loop circuit: A delay element generates a delayed clock signal which transitions with a delay from a rising (or falling) of a reference clock signal by a delay amount determined based on an output of a loop filter. A signal generation circuit generates two signals which complementarily change according to rising and...

20060176092 - Delay time adjusting method of delaying a phase of an output signal until a phase difference between an input signal and the output signal becomes an integral number of periods other than zero: A delay time adjusting method adjusts a delay time of an input signal so that a phase of the input signal and a phase of an output signal match each other. The delay time adjusting method comprises the step of delaying the phase of the output signal until a phase...

20060176090 - Delayed signal generation circuits and methods: Circuitry for delaying a signal includes a phase-locked loop comprising one or more output nodes for outputting one or more output signals in response to a reference signal. A buffer is coupled to the output nodes of the phase-locked loop for receiving phase-locked loop output signals and outputs one or...

20060176093 - Automatic gain control apparatus and method in an orthogonal frequency division multiple access sytem: An automatic gain control (AGC) apparatus of a wireless mobile terminal, and method, in an orthogonal frequency division multiple access (OFDMA) system. A gain amplifier controls an amplification gain of received analog symbols. An analog-to-digital converter converts the received analog symbols into a digital signal. A fast Fourier transform (FFT)...

20060176094 - Current-controlled cmos logic family: Various circuit techniques for implementing ultra high speed circuits use current-controlled CMOS (C3MOS) logic fabricated in conventional CMOS process technology. An entire family of logic elements including inverter/buffers, level shifters, NAND, NOR, XOR gates, latches, flip-flops and the like are implemented using C3MOS techniques. Optimum balance between power consumption and...

20060176095 - Cycle staging latch with dual phase dynamic outputs for hit logic compare: An output L1/L2 staging latch has dual rail inputs that up date the state of the L1 latch whenever the inputs are valid. Static outputs of the L1 latch are latched into the L2 by the L2 clock signal. The L2 latch has a static output that is available immediately,...

20060176096 - Power supply insensitive delay element: A power supply voltage insensitive delay element is provided that enables a digital signal to be delayed without variation due to power supply vulnerabilities. Current is limited through the transistors of the delay element using bias voltages produced by a bias voltage generator coupled to the delay element. The bias...

20060176097 - Method and apparatus for providing a fractional and integer pure digital programmable clock generator with temperature and process variation compensation algorithm: An apparatus and method for generating local clock signals from system clock signals based upon user inputs that provide a frequency multiplier and a frequency divider. The frequency multiplier and frequency divider are stored in an interface. System clock signals are received and local clock signals are generated by the...

20060176098 - Adaptive frequency compensation for dc-to-dc converter: One embodiment of the invention is a compensation circuit that includes a comparator that is coupled to receive a reference voltage. The compensation circuit can also include a capacitance coupled to receive a feedback voltage associated with an output voltage of a converter. Furthermore, the compensation circuit can include an...

20060176100 - Semiconductor integrated circuit: A semiconductor integrated circuit including: a circuit block including a MOS transistor that includes a bias input terminal, a source, and a substrate, in which the bias voltage is applied to the MOS transistor at a position of at least one of the source and the substrate through the bias...

20060176099 - Semiconductor integrated circuit and method of controlling the semiconductor integrated circuit: A semiconductor integrated circuit and a method of controlling the semiconductor integrated circuit are capable of performing low power consumption and an improvement in the operation speed. A variable higher reference voltage and a variable lower reference voltage are outputted from a voltage generator. The variable higher reference voltage is...

20060176101 - Semiconductor integrated circuit: In order to provide a semiconductor IC unit such as a microprocessor, etc. which satisfies both fast operation and lower power consumption properties with its high quality kept, the semiconductor IC unit of the present invention is composed so as to include a main circuit (LOG) provided with transistors, which...

20060176102 - Charge pump circuit: A charge pump circuit has a voltage increasing stage and a voltage decreasing stage in parallel, and sharing a common input. This shows charge to flow between the stages, so that charge used in the pumping of one stage is recycled to the other stage....

20060176103 - High voltage generating circuit and method and semiconductor memory device including the circuit: A first pump circuit is coupled to a first pump signal line and is configured to generate a first voltage greater than a power supply voltage at an output thereof responsive to transition of the first pump signal line from a ground voltage to the power supply voltage. A second...

20060176104 - Ultra wideband filter based on a pair of cross-coupled transistors: An ultra wideband filter is provided that filters an input signal using a pair of cross-coupled transistors with a small size and small power consumption. The ultra wideband filter includes a reference current generator unit generating a reference current using a bias signal of a predetermined level, a transconductor unit...

20060176105 - Amplifier, voltage stabilizing unit and method thereof: An amplifier, a voltage stabilizing unit and a method thereof. In the method, a determination may be made as to whether there is a current fluctuation in a signal, for example where the signal is a current output by at least one input unit. If the current fluctuation is detected,...

20060176106 - Current mode transconductor tuning device: A transconductor tuning device tuning a transconductance using a current. The transconductor tuning device includes a tuning section that applies a tuning current and a reference voltage to a transconductor converting an input voltage signal into a current signal and thereby tunes a level of transconductance. The tuning section includes...

20060170460 - Silicon-on-insulator sense amplifier for memory cell: A silicon-on-insulator (SOI) sense amplifier for sensing bit values stored in a memory cell, includes first and second input field effect transistors (FETs), connected to first and second cross-coupled CMOS inverter FET pairs. The input FETs are implemented as floating body FETs, which decreases gate capacitances and increases sense operation...

20060170461 - Comparator circuit having reduced pulse width distortion: A comparator circuit having reduced pulse width distortion includes a differential amplifier operative to receive at least first and second signals and to amplify a difference between the first and second signals. The differential amplifier generates a difference signal at an output thereof which is a function of the difference...

20060170462 - Reliability comparator with hysteresis: A comparator circuit includes a reference generator connecting to a first source providing a first voltage. The reference generator is operative to generate a reference signal and includes a control circuit selectively operable in at least a first mode or a second mode in response to a first control signal,...

20060170463 - Voltage-frequency conversion apparatus and method of generating reference voltage therefor: A voltage-frequency conversion apparatus which has a variable current source for charging a capacitor; a current amount adjustment unit that adjusts a current amount of the variable current source for charging the capacitor to be corresponding to a differential voltage between a first voltage and a second voltage; a comparator...

20060170464 - Synchronous frequency dividers and components therefor: The invention discloses a frequency divider using half-adding functions, comprising one latch circuitry with half adding function for each digit, each latch circuitry receiving its output signal Sout at its S-input, the latch circuitry (76) for the least significant bit receiving at its Carry-input a “1”, and each further latch...

20060170465 - Circuit for multiplying continuously varying signals: A means for obtaining an output signal which is the sum of the frequencies of two periodic input signals that may vary in amplitude and frequency over time. The apparatus, which provides means for realizing trigonometric functions of the form sin(α+β)=2 sin α cos β−sin(α−β) or sin nα=2 sin(n−1)α cos...

20060170466 - Adjustable start-up circuit for switching regulators: The adjustable start-up circuits basically include a sensor, a reference voltage, two stacked PMOS transistors, two stacked NMOS transistors, and a feedback line. The sensor compares a feedback voltage with a reference voltage. If the sensing voltage does not reach the reference voltage, the output voltage of the sensor turns...

20060170467 - Device for resetting an integrated circuit based on detection of a drop in the power supply voltage, and corresponding electronic circuit: A device is provided for resetting an integrated circuit generating a reset signal after a power supply voltage drop to a very low level has been detected. Such a device includes at least one control means, the state of which (conducting or non-conducting) is controlled by a control voltage equal...

20060170469 - Low power and low timing jitter phase-lock loop and method: A phase-lock loop generates an output clock signal from an input clock signal. The output clock signal is coupled through a clock tree and is fed back to a phase detector, which compares the phase of the output clock signal to the phase of the input clock signal. The output...

20060170468 - Pll circuit and program for same: A reference voltage signal (VpmpR), which is obtained by applying the output signal UPB/UP of a phase/frequency detection circuit (PFD) as a constantly locked state signal to a replica charge pump circuit (CPR) and then integrating, is compared in a correction voltage generation circuit (CMP) with a PLL circuit control...

20060170470 - Clock recovering circuit utilizing a delay locked loop for generating an output clock locked to an analog input signal and related method thereof: A clock recovering circuit for generating an output clock locked to an analog input signal includes: a phase detection unit for receiving the analog input signal and the output clock for generating a phase error signal according to the analog input signal and the output clock; a loop filter coupled...

20060170471 - Method and apparatus for initializing a delay locked loop: A delay locked loop includes initialization circuitry that ensures that a DLL is initialized to an operating point that is not to close to either end of a delay vs. control voltage characteristic. The initialization circuitry forces the DLL to initially search for a lock point starting from an initial...

20060170472 - Variable delay circuit: A variable delay circuit includes plural stages of first variable delay elements coupled in series for sequentially delaying a reference clock signal or a data signal, a second variable delay element coupled in parallel to the plural stages of first variable delay elements for delaying the reference clock signal, a...

20060170473 - Method of controlling slope and dead time in an integrated output buffer with inductive load: A method and apparatus independently controls the increasing rate and the decreasing rate a P-channel power FET and an N-channel power FET driving an inductive load. Circuits inhibit turning ON the P-channel FET until the voltage on the gate of the N-channel FET falls below its turn-on voltage threshold, and...

20060170474 - Duty cycle corrector: A duty cycle corrector comprising a first circuit and a second circuit. The first circuit is configured to receive a clock signal and an inverted clock signal and to obtain a delay signal that indicates a time difference between transitions of the clock signal and the inverted clock signal. The...

20060170475 - Duty detection circuit: The duty detection circuit (100) comprises an integration circuit (110) for receiving an RCLK signal and an FCLK signal that are internal clock signals generated by a DLL circuit, and generating voltage levels (DB signal and VREF signal) in accordance with the duty ratio of these internal clock signals; an...

20060170476 - Delay circuit for synchronizing arrival of a clock signal at different circuit board points: A clock signal generation system and method to distribute at least one clock signal to a plurality of points on a circuit board using a plurality of digitally programmable delay circuits each of which delays the clock signal by a desired amount so as to synchronize arrival of the clock...

20060170477 - Semiconductor integrated circuit having output circuit: A semiconductor integrated circuit that has an output circuit in which an output-stage operating voltage lower than a power supply voltage is applied to an output stage is provided. Even when the power supply voltage is lowered, a sufficient output signal amplitude can be obtained. An increase in circuit scale...

20060170478 - Delay circuit for semiconductor device: A delay circuit for a semiconductor device includes a variable resistor unit having a resistance value adjusted in response to a control signal, and a variable load unit having a capacitance value adjusted in response to the control signal. The delay circuit of the present invention includes a variable resistor...

20060170479 - Clock supply circuit: The clock supply circuit of the present invention comprises a plurality of clock supply paths and a clock gate circuit. The clock supply paths branch a clock signal and supply each of the branched clock signals to a plurality of sequential circuits via a buffer. The clock gate circuit is...

20060170480 - Apparatus and method for low power clock distribution: A clock distribution apparatus for providing a local clock signal having a first voltage swing to a circuit unit being on a same substrate includes a global clock distribution network for generating and distributing a global clock signal having a second voltage swing being less than the first voltage swing;...

20060170481 - Low-swing level shifter: In general, in one aspect, the disclosure describes an apparatus for shifting a low swing signal. The apparatus includes a first pair of transistors to receive a first input signal and a second input signal and to generate a first output signal that is a shifted version of the first...

20060170482 - Digitally programmable delay circuit with process point tracking: A digitally programmable delay circuit comprising a plurality of transistors connected in parallel with each other and to a line carrying a signal having an edge to be delayed. One or more of the transistors are selected by a delay control signal to impose a delay amount to the edge,...

20060170483 - Integrated circuit: An integrated circuit produced from non-monocrystalline semiconductors, including a plurality of transistors, all of the transistors being of the same type, and at least two timer signal inputs, wherein the timer signals fed to the different inputs are temporally non-overlapping signals....

20060170484 - Semiconductor device: A semiconductor device with a blind scheme for boosting an internal voltage using an external supply voltage is disclosed. The semiconductor device includes a voltage detector for detecting a voltage level of the external supply voltage being applied to the semiconductor device, a pulse generator for being controlled by a...

20060170485 - Integrated charge pump: An integrated charge pump is provided, comprising: a pump capacitor having a first terminal and a second terminal; a control unit, which operates the charge pump in an alternation between a first phase and a second phase; a first switching device in order to charge the pump capacitor with a...

20060170486 - Pulse generator having an efficient fractional voltage converter and method of use: Disclosed are systems and methods which provide voltage conversion in increments less than integer multiples of a power supply (e.g., battery) voltage. A representative embodiment provides power supply voltage multipliers in a binary ladder distribution to provide a desired number of output voltage steps using a relatively uncomplicated circuit design....

20060170487 - A voltage reference circuit for ultra-thin oxide technology and low voltage applications: A precision voltage reference for ultra-thin gate oxide process technologies is realized with a network of tunneling current circuit elements. A voltage difference is measured between selected nodes of one or more current paths of a voltage divider. The tunneling current circuit element may be implemented with any suitable device,...

20060170488 - Reference voltage generation circuit: A circuit of generation of a reference voltage by a first MOS transistor of a first type connected to a first terminal of application of a supply voltage. The first transistor is connected with a second MOS transistor of the same type controlled by an input stage of a transconductance...

20060170489 - Fast dynamic low-voltage current mirror with compensated error: A current mirror comprising: a current source; a first p-channel MOS transistor having a source coupled to an operating potential, and a gate and a drain coupled to the current source; a second p-channel MOS transistor having a source coupled to the operating potential, a gate coupled to the gate...

20060170490 - Fast dynamic low-voltage current mirror with compensated error: A current mirror comprising: current source; a first p-channel transistor having a source coupled to operating potential, and a gate and drain coupled to current source; a second p-channel transistor having a source coupled to operating potential, a gate coupled to gate of first p-channel transistor, and a drain; a...