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01/25/07 | 69 views | #20070020774 | Prev - Next | USPTO Class 438 | About this Page  438 rss/xml feed  monitor keywords

Methods of utilizing magnetoresistive memory constructions

USPTO Application #: 20070020774
Title: Methods of utilizing magnetoresistive memory constructions
Abstract: The invention includes a method of forming a magnetoresistive memory device having a memory bit stack. The stack includes a first magnetic layer, a second magnetic layer, and a non-magnetic layer between the first and second magnetic layers. A first conductive line is proximate the stack and configured for utilization in reading information from the memory bit. The first conductive line is ohmically connecting with either the first or second magnetic layer. A second conductive line is spaced from the stack by a sufficient distance that the second conductive line is not ohmically connected to the stack, and is configured for utilization in writing information to the memory bit. The invention also includes methods of storing and retrieving information. (end of abstract)
Agent: Wells St. John P.s. - Spokane, WA, US
Inventor: Hasan Nejad
USPTO Applicaton #: 20070020774 - Class: 438003000 (USPTO)
Related Patent Categories: Semiconductor Device Manufacturing: Process, Having Magnetic Or Ferroelectric Component
The Patent Description & Claims data below is from USPTO Patent Application 20070020774.
Brief Patent Description - Full Patent Description - Patent Application Claims  monitor keywords

RELATED PATENT DATA

[0001] This patent is a divisional application of U.S. patent application Ser. No. 10/915,931, filed Aug. 10, 2004, entitled "Magnetoresistive Memory Devices and Assemblies; and Methods of Storing and Retrieving Information", naming Hasan Nejad as inventor, which is a divisional application of U.S. patent application Ser. No. 10/418,406, filed Apr. 18, 2003, now U.S. Pat. No. 6,791,870, which is a divisional application of U.S. patent application Ser. No. 10/051,679, filed Jan. 16, 2002, now U.S. Pat. No. 6,735,111.

TECHNICAL FIELD

[0002] The invention pertains to magnetoresistive memory devices, such as, for example, magnetic random access memory (MRAM) devices, and also pertains to methods of storing and retrieving information.

BACKGROUND OF THE INVENTION

[0003] Numerous types of digital memories are utilized in computer system components, digital processing systems, and other applications for storing and retrieving data. MRAM is a type of digital memory in which digital bits of information comprise alternative states of magnetization of magnetic materials in memory cells. The magnetic materials can be thin ferromagnetic films. Information can be stored and retrieved from the memory devices by inductive sensing to determine a magnetization state of the devices, or by magnetoresistive sensing of the magnetization states of the memory devices. It is noted that the term "magnetoresistive device" characterizes the device and not the access device, and accordingly a magnetoresistive device can be accessed by, for example, either inductive sensing or magnetoresistive sensing methodologies.

[0004] A significant amount of research is currently being invested in magnetic digital memories, such as, for example, MRAM's, because such memories are seen to have significant potential advantages relative to the dynamic random access memory (DRAM) components and static random access memory (SRAM) components that are presently in widespread use. For instance, a problem with DRAM is that it relies on electric charge storage within capacitors. Such capacitors leak electric charge, and must be refreshed at approximately 64-128 millisecond intervals. The constant refreshing of DRAM devices can drain energy from batteries utilized to power the devices, and can lead to problems with lost data since information stored in the DRAM devices is lost when power to the devices is shut down.

[0005] SRAM devices can avoid some of the problems associated with DRAM devices, in that SRAM devices do not require constant refreshing. Further, SRAM devices are typically faster than DRAM devices. However, SRAM devices take up more semiconductor real estate than do DRAM devices. As continuing efforts are made to increase the density of memory devices, semiconductor real estate becomes increasingly valuable. Accordingly, SRAM technologies are difficult to incorporate as standard memory devices in memory arrays.

[0006] MRAM devices have the potential to alleviate the problems associated with DRAM devices and SRAM devices. Specifically, MRAM devices do not require constant refreshing, but instead store data in stable magnetic states. Further, the data stored in MRAM devices will remain within the devices even if power to the devices is shutdown or lost. Additionally, MRAM devices can potentially be formed to utilize less than or equal to the amount of semiconductor real estate associated with DRAM devices, and can accordingly potentially be more economical to incorporate into large memory arrays than are SRAM devices.

[0007] Although MRAM devices have potential to be utilized as digital memory devices, they are currently not widely utilized. Several problems associated with MRAM technologies remain to be addressed. It would be desirable to develop improved MRAM devices.

SUMMARY OF THE INVENTION

[0008] In one aspect, the invention encompasses a magnetoresistive memory device. The device includes a memory bit which comprises a stack having a first magnetic layer, a second magnetic layer, and a non-magnetic layer between the first and second magnetic layers. A first conductive line is proximate the stack and configured for utilization in reading information from the memory bit. A second conductive line is spaced from the stack by a greater distance than the first conductive line is spaced from the stack, and is configured for utilization in writing information to the memory bit.

[0009] In one aspect, the invention encompasses a magnetoresistive memory device assembly. The assembly includes an array of individual magnetoresistive memory devices. The devices include memory bits. The individual memory bits comprise a stack of a pair of magnetic layers separated by a non-magnetic layer. A first conductive line is proximate the stack and utilized for reading information from the memory bit. A second conductive line is spaced from the stack by a greater distance than the first conductive line and is configured for utilization in writing information to the memory bit. The first conductive line extends across a first set of several of the individual magnetoresistive memory devices of the array, and the second conductive line also extends across the first set of the individual magnetoresistive memory devices of the array. A first transistor is electrically connected with the first conductive line and accordingly electrically connected with the first set of individual magnetoresistive memory devices. Additionally, a second transistor is electrically connected with the second conductive line, and accordingly electrically connected with the first set of the individual magnetoresistive memory devices of the array.

[0010] In one aspect, the invention encompasses a method of storing and retrieving information. A magnetoresistive memory device is provided. The device comprises a memory stack having a pair of magnetic layers separated by a non-magnetic layer. A first conductive line is provided proximate the stack and utilized for reading information from the memory bit, and a second conductive line is spaced from the stack by a greater distance than the first conductive line and utilized for writing information to the memory bit. The first conductive line is operated at a maximum amperage of from about 500 nanoamps to about 1 microamp during reading of information from the memory bit, and the second conductive line is operated at a maximum amperage of from about 1 milliamp to about 10 milliamps during writing of information to the memory bit.

BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Preferred embodiments of the invention are described below with reference to the following accompanying drawings.

[0012] FIG. 1 is a diagrammatic, cross-sectional view of an exemplary magnetoresistive memory device encompassed by the present invention.

[0013] FIG. 2 is a diagrammatic top view of a fragment of a magnetoresistive memory device assembly illustrating an exemplary application of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014] In one aspect, the invention pertains to a novel MRAM device exemplified by a construction 10 in FIG. 1. Construction 10 includes a substrate 12. Substrate 12 can comprise, for example, monocrystalline silicon having various circuit elements (not shown) formed thereover. To aid in interpretation of the claims that follow, the terms "semiconductive substrate" and "semiconductor substrate" are defined to mean any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other materials). The term "substrate" refers to any supporting structure, including, but not limited to, the semiconductive substrates described above.

[0015] An electrically conductive line 14 is supported by substrate 12, an electrically insulative layer 16 is over line 14, and an electrically conductive line 18 is over electrically insulative layer 16. In the discussion and claims that follow, conductive line 18 can be referred to as a first conductive line, and conductive line 14 can be referred to as a second conductive line. Conductive lines 14 and 18 can comprise any of numerous conductive materials, including, for example, metals, metal compositions, and conductively-doped semiconductive materials. Insulative layer 16 can comprise any of numerous electrically insulative materials, including, for example, silicon dioxide, silicon nitride, and/or so-called low-k materials.

[0016] A memory bit 20 is over conductive line 18, and comprises a stack which includes a first magnetic layer 22, a second magnetic layer 24, and a non-magnetic material 26 between magnetic layers 22 and 24. Magnetic layers 22 and 24 of memory bit 20 typically comprise one or more of nickel, iron, cobalt, iridium, manganese, platinum and ruthenium. The non-magnetic material 26 can comprise either an electrically conductive material (such as copper) in applications in which the MRAM is to be a giant magnetoresistive (GMR) device, or can comprise an electrically insulative material (such as, for example, aluminum oxide (Al.sub.2O.sub.3) or silicon dioxide), in applications in which the MRAM device is to be a tunnel magnetoresistive (TMR) device. Magnetic layer 24 physically contacts conductive line 18 in the shown embodiment.

[0017] A third conductive line 28 is provided over the memory bit, and extends in an orthogonal orientation relative to first and second conductive lines 18 and 14. Accordingly, third conductive line 28 extends into and out of the page in the shown orientation of construction 10. Conductive line 28 can comprise any of numerous conductive materials, including, for example, metals and metal compositions. Conductive line 28 physical contacts magnetic layer 22 in the shown embodiment.

[0018] An electrically insulative material 30 is provided along sidewalls of conductive line 28 and memory bit 20, as well as over a top of second conductive line 18. Insulative material 30 can comprise any of numerous electrical insulative materials, including, for example, silicon dioxide, silicon nitride, and borophosphosilicate glass (BPSG).

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