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Methods of measuring frequencies including charging electrical circuitsRelated Patent Categories: Data Processing: Measuring, Calibrating, Or Testing, Measurement System In A Specific Environment, Electrical Signal Parameter Measurement System, Waveform Analysis, FrequencyMethods of measuring frequencies including charging electrical circuits description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20070185670, Methods of measuring frequencies including charging electrical circuits. Brief Patent Description - Full Patent Description - Patent Application Claims
CROSS-REFERENCE TO RELATED APPLICATION [0001] This application claims priority to and is a continuation of application Ser. No. 11/031,104, filed Jan. 7, 2005, which claims priority from Korean Patent Application No. 2004-11576, filed Feb. 20, 2004. The disclosures of the above referenced U.S. and Korean applications are hereby incorporated herein by reference in their entirety. FIELD OF THE INVENTION [0002] The present invention relates to electronic devices, and more particularly, to frequency measuring circuits and related methods. BACKGROUND [0003] A semiconductor memory device may receive clock signals having different frequencies. Internal circuits of the semiconductor memory device may not show a same performance for all frequencies and may thus need to perform operations depending on a frequency of an input clock signal. For example, a delay locked loop (DLL) may be used to generate an internal clock signal which is synchronized with a clock signal input from an external portion. In this case, the internal clock signal can be synchronized with the external clock signal even though a delay circuit having a short delay time is used if a frequency of the external clock signal is high. When a frequency of the external clock signal is low, however, the internal clock signal may be synchronized with the external clock signal only if a delay circuit having a relatively long delay time is used. An awareness of a frequency information of the input clock signal may be used to improve frequency characteristics of the internal circuits of the semiconductor memory device. [0004] A conventional semiconductor memory device may use a CL (CAS latency) value set by a user as frequency information for a clock signal. FIG. 1 is a block diagram illustrating a circuit used when different delays are used according to a frequency of a clock signal in a conventional semiconductor memory device. Functions and operations of components of FIG. 1 are explained below. [0005] One of a first delay circuit 10 and a second delay circuit 20 is selected according to a CL value, and an output signal OUT is generated by delaying an input signal IN by a predetermined time period. That is, in a conventional semiconductor memory device, a CL value is set differently according to a frequency of the input clock signal, and a generation time point of internally generated signals depends on a frequency of the input clock signal. Therefore, if a user sets a CL value according to a frequency of a clock signal to be used, the circuit of FIG. 1 selects the first delay circuit 10 or the second delay circuit 12 according to the CL value to make a generation time point of the output signal OUT. [0006] FIG. 2 is a block diagram illustrating a method of adjusting a delay time of a delay circuit according to a frequency of an externally input clock signal in the delay locked loop (DLL) of the conventional semiconductor memory device. In FIG. 2, a third delay circuit 20 and a fourth delay circuit 22 may each have multiple different delay circuits. [0007] A delay locked loop (DLL) may be used to synchronize an internal clock signal with an external clock signal in a semiconductor memory device. As described above, if a delay locked loop is used in a semiconductor memory device, the internal clock signal can be synchronized with the external clock signal even though a delay circuit having a short delay time is used when a frequency of the external clock signal is high. In contrast, a delay circuit having a relatively long delay time may be needed when a frequency of the external clock signal is low. The semiconductor memory device of FIG. 2 generates a relatively short delay time period by cutting a second fuse 24 using a CL value set by a user for the third delay circuit 20 to generate the internal clock signal and for the fourth delay circuit 22 to not operate when a frequency of a clock signal is high. The semiconductor memory device of FIG. 2 generates a relatively long delay time period such that the internal clock signal is generated through both the third delay circuit 20 and the fourth delay circuit 22 without cutting the first and second fuses 24 and 26. [0008] If a CL value is used as frequency information for a clock signal, however, there may be a problem in that a user should change a CL value whenever a frequency of a clock signal input to the semiconductor memory device is varied. The semiconductor memory device may operate abnormally if a user makes a mistake in setting a CL value. SUMMARY OF THE INVENTION [0009] According to some embodiments of the present invention, a frequency measuring circuit may include an edge detector, a charge pump, and an analog-to-digital converter. The edge detector may be configured to generate an output pulse responsive to an edge of an input clock signal. The charge pump may be configured to generate an output signal responsive to the output pulse from the edge detector. The analog-to-digital (A/D) converter may be configured to convert the output signal into a digital value representing a frequency of the input clock signal. [0010] In addition, an encoder may be configured to convert the digital value into a frequency information signal representing a frequency of the input clock signal. More particularly, the frequency information signal may have a first value when the frequency of the input clock signal is less than a first threshold, a second value when the frequency of the input clock signal is less than a second threshold and greater than or equal to the first threshold, and a third value when the frequency of the input clock signal is greater than or equal to the second threshold. [0011] The edge detector may be configured to generate the output pulse responsive to rising and falling edges of the input clock signal. Moreover, the edge detector may include a delay circuit and a logic circuit. The delay circuit may be configured to generate a delayed clock signal by delaying the clock signal by a time period. The logic circuit may be configured to combine the clock signal and the delayed clock signal to generate the output pulse. More particularly, the delay circuit may include a plurality of serially connected inverters, and the logic circuit may include an exclusive OR gate having a first input coupled to the clock signal and a second input coupled to the delayed clock signal. The edge detector may be configured to generate the output pulse responsive to each rising and falling edge of the input clock signal, and each output pulse from the edge detector may have a same duration. [0012] The charge pump may include a capacitor and a charging transistor coupled in series between a power supply and the capacitor. The charging transistor may be configured to charge the capacitor responsive to the output pulse from the edge detector. The charge pump may also include a discharge circuit configured to discharge the capacitor. [0013] The analog-to-digital (A/D) converter may include a plurality of resistors and a plurality of comparators. The plurality of resistors may be connected in series between a power supply voltage and a reference voltage, and the plurality of serially connected resistors may be configured to provide a plurality of reference voltages. A first input of each comparator may be coupled to a respective one of the reference voltages and a second input of each comparator may be coupled to the output signal from the charge pump. [0014] The analog-to-digital (A/D) converter may be a flash converter configured to convert the output signal into a thermometer code type digital value. In addition, an internal clock signal generator may be configured to generate an internal clock signal for memory operations responsive to the digital value representing the frequency of the input clock signal. [0015] According to additional embodiments of the present invention, a method of measuring a frequency of an input clock signal may include generating an output pulse responsive to an edge of the input clock signal. A circuit may be charged responsive to the output pulse from the edge detector, and an output signal from the charged circuit may be converted into a digital value representing a frequency of the input clock signal. [0016] In addition, the digital value may be converted into a frequency information signal representing a frequency of the input clock signal. More particularly, the frequency information signal may have a first value when the frequency of the input clock signal is less than a first threshold, a second value when the frequency of the input clock signal is less than a second threshold and greater than or equal to the first threshold, and a third value when the frequency of the input clock signal is greater than or equal to the second threshold. [0017] Generating the output pulse may include generating the output pulse responsive to rising and failing edges of the input clock signal. More particularly, generating the output pulse may include delaying the clock signal by a time period to generate a delayed clock signal, and combining the clock signal and the delayed clock signal to generate the output pulse. Combining the clock signal and the delayed clock signal may include performing an exclusive OR operation on the clock signal and on the delayed clock signal. Generating the output pulse may include generating the output pulse responsive to each rising and falling edge of the input clock signal, and each output pulse may have a same duration. [0018] Charging the circuit may include charging a capacitor responsive to the output pulse, and the digital value representing a frequency of the input clock may be a thermometer code type digital value. In addition, an internal clock signal may be generated for memory operations responsive to the digital value representing the frequency of the input clock signal. [0019] According to yet additional embodiments of the present invention, an integrated circuit memory device may include a frequency measuring circuit, an internal clock signal generator, and a memory cell array. The frequency measuring circuit may include an edge detector configured to generate an output pulse responsive to an edge of an input clock signal, a charge pump configured to generate an output signal responsive to the output pulse from the edge detector, and an analog-to-digital (A/D) converter configured to convert the output signal into a digital value representing a frequency of the input clock signal. The internal clock signal generator may be configured to generate an internal clock signal responsive to the digital value representing the frequency of the input clock signal. The memory cell array may be configured to perform read and/or write operations responsive to the digital value representing the frequency of the input clock signal. [0020] More particularly, the edge detector may be configured to generate the output pulse responsive to rising and falling edges of the input clock signal. The edge detector may include a delay circuit and a logic circuit. The delay circuit may be configured to generate a delayed clock signal by delaying the clock signal by a time period. The logic circuit may be configured to combine the clock signal and the delayed clock signal to generate the output pulse. Continue reading about Methods of measuring frequencies including charging electrical circuits... Full patent description for Methods of measuring frequencies including charging electrical circuits Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Methods of measuring frequencies including charging electrical circuits patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. 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