| Methods of manufacturing semiconductor devices having buried bit lines -> Monitor Keywords |
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Methods of manufacturing semiconductor devices having buried bit linesRelated Patent Categories: Semiconductor Device Manufacturing: Process, Making Field Effect Device Having Pair Of Active Regions Separated By Gate Structure By Formation Or Alteration Of Semiconductive Active Regions, Having Insulated Gate (e.g., Igfet, Misfet, Mosfet, Etc.), Having Additional Gate Electrode Surrounded By Dielectric (i.e., Floating Gate), Multiple Interelectrode Dielectrics Or Nonsilicon Compound Gate InsulatorMethods of manufacturing semiconductor devices having buried bit lines description/claimsThe Patent Description & Claims data below is from USPTO Patent Application 20070190725, Methods of manufacturing semiconductor devices having buried bit lines. Brief Patent Description - Full Patent Description - Patent Application Claims
PRIORITY CLAIM AND CROSS REFERENCE TO RELATED APPLICATION [0001] This application is a divisional of U.S. patent application Ser. No. 11/240,544, filed on Sep. 30, 2005 and claims priority under 35 U.S.C. .sctn. 119 to Korean Patent Application No. 10-2004-0107993, filed on Dec. 17, 2004, in the Korean Intellectual Property Office, the disclosures of both are incorporated herein by reference in their entirety. FIELD OF THE INVENTION [0002] The present invention relates to semiconductor devices and methods of manufacturing semiconductor devices, and more particularly to semiconductor devices having buried bit lines and methods of manufacturing semiconductor devices having buried bit lines. BACKGROUND [0003] In a semiconductor device such as a non-volatile memory device having buried bit lines, an impurity may be selectively doped in upper portions of a semiconductor substrate to form buried bit lines in the substrate which are spaced uniformly from one another. A buried bit line formed directly in a semiconductor substrate may require minimal space. [0004] FIG. 1 is a plan view of a conventional NOR device with a SONOS structure having buried bit lines. Bit lines 12 are formed in upper portions of a semiconductor substrate 10 doped with an impurity of a first conductivity type, e.g., a P-type impurity, by selectively doping the substrate with an impurity, e.g., an N-type impurity, of a second conductivity type opposite to that of the semiconductor substrate 10. Bit lines 12 may have a higher net doping concentration than substrate 10 and may be spaced uniformly from one another while extending in a first direction (e.g. the Y-axis direction indicated in FIG. 1). The bit lines 12 may have a stripe pattern. The word lines 14 may be formed at right angles to the bit lines 12. The word lines 14 may be spaced uniformly from one another and may cover portions of the semiconductor substrate 10 and the bit lines 12. The word lines 14 may be shaped as stripes and may cover channel regions 16 formed in the upper portions of the semiconductor substrate 10 and source/drain regions 18 formed in the bit lines 12. Bit line contacts 20 for external electrical connection may be formed at one end of the bit lines 12. [0005] In some conventional semiconductor devices having buried bit lines, device isolation of the bit lines 12 is performed by PN junctions between the bit lines and the semiconductor substrate 10, which have opposite conductivity types. However, as semiconductor devices are miniaturized, punch-through (i.e. a breakdown due to overlapping junction depletion regions) may occur at the PN junction, resulting in a loss of device isolation. That is, as the distance between adjacent bit lines is reduced in an effort to make devices smaller, the effectiveness of PN junction isolation as a means to isolate adjacent devices may be reduced. [0006] Furthermore, with the high integration of semiconductor devices, the gate channel length is decreased. This may result in several problems, such as a short channel effects, microscopic pattern formation, and restricted operating speed. In particular, various short channel effects may become a serious problem. For example, an increased electric field around the drain region may cause punch-through that penetrates to the potential barrier around a source region. Also, thermo-electrons may cause avalanche breakdown, and a vertical electric field may decrease the vertical mobility of carriers. SUMMARY [0007] According to some embodiments of the invention, a semiconductor device includes a semiconductor substrate having a first conductivity type, a pair of bit lines extending in a first direction and doped with an impurity of a second conductivity type opposite to the first conductivity type and spaced from one another in an upper portion of the semiconductor substrate, a first line formed between the pair of bit lines having a plurality of alternating recessed device isolation regions and channel regions, with each of the channel regions contacting each bit line of the at least one pair of bit lines, and word lines formed at right angles to the first lines and covering the channel regions. [0008] In some embodiments of the invention, the first conductivity type is P-type and the second conductivity type is N-type. [0009] In some embodiments of the invention, the recessed isolation regions may isolate the at least one pair of bit lines from one another. The recessed isolation regions may further isolate adjacent pairs of channel regions from one another. [0010] In some embodiments of the invention, each of the channel regions includes an upper surface and a pair of opposing sidewalls. An ONO layer is formed on the sidewalls and on the upper surface of the channel region, and a gate electrode is formed on the ONO layer. In some embodiments, the ONO layer and the gate electrode layer extend onto the upper surfaces of adjacent bit lines. The device isolation regions may be filled with HDP oxide and may extend into the substrate. [0011] Some embodiments of the invention include an insulating layer formed in the recess regions and covering surface portions of each of the bit lines. A bit line contact may be formed through the insulating layer for providing electrical contact to at least one of the bit lines. [0012] In some embodiments of the invention, a filling layer is formed partially filling each of the recess regions, and the ONO layer is at least partially formed on the filling layer. The filling layer may include an HDP oxide, TEOS, USG or a PECVD oxide. [0013] Some embodiments of the invention provide a unit cell of a semiconductor memory device having a semiconductor substrate, a pair of bit lines doped with an impurity having conductivity type opposite to that of the substrate and spaced from one another in the upper portion of the semiconductor substrate, a channel region between the pair of bit lines, the channel region having an upper surface and a pair of opposing side surfaces, a pair of recess regions adjacent the opposing side surfaces of the channel region and separating the pair of bit lines on either side of the channel region, an ONO layer formed on the bit lines and the upper and side surfaces of the channel region, and a gate electrode formed on the ONO layer above the upper surface and side surfaces of the channel region. [0014] In some embodiments, the unit cell may have an insulating layer formed in the recess regions and covering surface portions of each of the bit lines, and a bit line contact extending through the insulating layer for providing electrical contact to at least one of the bit lines. [0015] Some embodiments of the invention include a filling layer partially filling each of the recess regions, wherein the ONO layer is at least partially formed on the filling layer. The filling layer may include an HDP oxide, TEOS, USG or a PECVD oxide. [0016] According to some embodiments of the invention, methods of forming a semiconductor device include forming a plurality of bit lines spaced from one another and extending in a first direction in an upper portion of a semiconductor substrate having a first conductivity type, by selectively doping an upper portion of the substrate with an impurity of a second conductivity type that is opposite to first conductivity type. A mask layer is formed on a surface of the semiconductor substrate above the upper portion of the substrate, and a plurality of spaced apart recess regions are formed between the bit lines. The recess regions may extend through the mask layer and into the substrate. [0017] Methods according to the invention further include depositing a first filling layer in the recess regions, removing the mask layer to expose the surface of the semiconductor substrate, partially removing the first filling layer from the semiconductor substrate, to form a second filling layer exposing sidewalls of the recess regions. The first filling layer may include an HDP oxide, TEOS, USG or a PECVD oxide. An ONO layer is formed on the surface of the semiconductor substrate including the sidewalls of the recess regions and the second filling layer, and a gate electrode layer is formed on the ONO layer over the sidewalls of the recess regions extending between adjacent pairs of bit lines. Accordingly, in some embodiments, the channel width may be determined by the height of the second filling layer. [0018] In some embodiments, forming a plurality of spaced apart recess regions defines a plurality of channel regions extending between adjacent pairs of bit lines. The ONO layer covers the plurality of channel regions. [0019] In some embodiments, forming the recess regions includes forming a photoresist pattern for defining the recess regions on the mask layer, and partially removing the mask layer and the semiconductor substrate in the shape of the photoresist pattern to form the recess regions. [0020] In some embodiments, the ONO layer may serves as an etch stop layer when forming the gate electrode. Continue reading about Methods of manufacturing semiconductor devices having buried bit lines... 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