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  Methods of implementing and enhanced silicon-on-insulator (soi) box structuresUSPTO Application #: 20060234428Title: Methods of implementing and enhanced silicon-on-insulator (soi) box structures Abstract: Enhanced silicon-on-insulator (SOI) buried oxide (BOX) structures and methods are provided for implementing enhanced SOI BOX structures. An oxygen implant step is performed from a backside into a thinned silicon substrate layer. An anneal step forms thick buried oxide (BOX) regions from oxygen implants in the silicon substrate layer. The oxygen implant step forms an isolated region near the oxygen implants. A backside implant step selectively dopes the isolated region for forming a backgate for an SOI device being formed including a selected one of anti-fuse (AF) devices, and SOI transistors including PFET and NFET devices. (end of abstract) Agent: Ibm Corporation RochesterIPLaw Dept 917 - Rochester, MN, US Inventors: Toshiharu Furukawa, Carl John Radens, William Robert Tonti, Richard Quimby Williams USPTO Applicaton #: 20060234428 - Class: 438149000 (USPTO) Related Patent Categories: Semiconductor Device Manufacturing: Process, Making Field Effect Device Having Pair Of Active Regions Separated By Gate Structure By Formation Or Alteration Of Semiconductive Active Regions, On Insulating Substrate Or Layer (e.g., Tft, Etc.) The Patent Description & Claims data below is from USPTO Patent Application 20060234428. Brief Patent Description - Full Patent Description - Patent Application Claims
FIELD OF THE INVENTION [0001] The present invention relates generally to the field of semiconductor manufacturing and, more specifically, to enhanced silicon-on-insulator (SOI) buried oxide (BOX) structures and methods for implementing enhanced SOI BOX structures. DESCRIPTION OF THE RELATED ART [0002] Silicon-on-insulator (SOI) transistors provide better performance at low operating voltages than do transistors of similar dimensions fabricated in bulk silicon substrates. Superior performance of SOI transistors at low operating voltage is related to the relatively lower junction capacitances obtained on an SOI device as compared to a bulk silicon device of similar dimensions. A buried oxide layer in an SOI device separates active transistor regions from the bulk silicon substrate, reducing junction capacitance. [0003] Various SOI transistor arrangements are known. For example, Wei et al., U.S. patent application Publication No. US 2003/0223258 published Dec. 4, 2003, and assigned to the present assignee, discloses a method comprising forming a gate electrode above an SOI substrate comprised of a bulk substrate, a buried insulation layer and an active layer, the gate electrode having a protective layer formed thereabove, and forming a plurality of dielectric regions in the bulk substrate after the gate electrode is formed, the dielectric regions being self-aligned with respect to the gate electrode, the dielectric regions having a dielectric constant that is less than a dielectric constant of the bulk substrate. In other embodiments, the method comprises forming a gate electrode above an SOI substrate comprised of a bulk substrate, a buried insulation layer and an active layer, the gate electrode having a protective layer formed thereabove, performing at least one oxygen implant process after the gate electrode and the protective layer are formed to introduce oxygen atoms into the bulk substrate to thereby form a plurality of oxygen-doped regions in the bulk substrate, and performing at least one anneal process to convert the oxygen-doped regions to dielectric regions comprised of silicon dioxide in the bulk substrate. In one illustrative embodiment, the device comprises a gate electrode formed above an SOI structure comprised of a bulk substrate, a buried insulation layer, and an active layer, and a plurality of dielectric regions comprised of silicon dioxide formed in the bulk substrate, the dielectric regions being self-aligned with respect to the gate electrode. [0004] While the above disclosed methods and silicon-on-insulator (SOI) structures provide improvements over prior art arrangements, a need exists for enhanced SOI devices and methods for manufacturing thereof. It is desirable to provide new backgate processing techniques and enhanced SOI BOX structures. SUMMARY OF THE INVENTION [0005] Principal aspects of the present invention are to provide enhanced silicon-on-insulator (SOI) buried oxide (BOX) structures and methods for implementing enhanced SOI BOX structures. Other important aspects of the present invention are to provide such enhanced silicon-on-insulator (SOI) buried oxide (BOX) structures and methods for implementing enhanced SOI BOX structures substantially without negative effect and that overcome many of the disadvantages of prior art arrangements. [0006] In brief, enhanced silicon-on-insulator (SOI) buried oxide (BOX) structures and methods are provided for implementing enhanced SOI BOX structures. [0007] In accordance with one embodiment of the invention, a silicon-on-insulator (SOI) structure is provided including a silicon substrate layer, a thin buried oxide (BOX) layer carried by the silicon substrate layer, an active layer carried by the thin BOX layer, and a pad oxide layer carried by the active layer. The silicon substrate layer is thinned and an oxygen implant step is performed from the backside into the thinned silicon substrate layer. An anneal step forms thick buried oxide (BOX) regions from oxygen implants in the silicon substrate layer. [0008] In accordance with features of one embodiment of the invention, the oxygen implant step forms an isolated region near the oxygen implants. A backside implant step selectively dopes the isolated region for forming a backgate for an SOI device being formed including a selected one of anti-fuse (AF) devices, and SOI transistors including PFET and NFET devices. [0009] In accordance with features of one embodiment of the invention, a gate oxide and a gate electrode are formed over the active region above the backgate. Doping, formation and activation of each respective source/drain region and the gate electrode are provided for the SOI transistor [0010] In accordance with features of one embodiment of the invention, an image of the gate electrode is larger than a backgate image, whereby gate alignment problems of the SOI transistor are minimized. A programmable body contact is provided, for example, by applying a first voltage supply potential between the source/drain regions and the backgate and applying a second voltage supply potential between the gate electrode and ground, where the first voltage supply potential is greater than the second voltage supply potential. [0011] In accordance with features of one embodiment of the invention, a doping implant into the active layer above the backgate forms a doped plate region from the active layer. A contact formation on the backgate and doped plate region provides respective anti-fuse (AF) connections. A voltage supply source is connected between the respective anti-fuse (AF) connections in a fuse programming step forming a conduction path between the backgate and doped plate region. BRIEF DESCRIPTION OF THE DRAWINGS [0012] The present invention together with the above and other objects and advantages may best be understood from the following detailed description of the preferred embodiments of the invention illustrated in the drawings, wherein: [0013] FIGS. 1-3, 4A and 4B are diagrams not to scale illustrating exemplary steps for implementing enhanced SOI BOX structures in accordance with one preferred embodiment; [0014] FIG. 5 is a diagram not to scale illustrating further exemplary steps for implementing silicon-on-insulator (SOI) transistor processing on the enhanced SOI BOX structure of FIG. 4A in accordance with one preferred embodiment; [0015] FIG. 6 is a diagram not to scale illustrating further exemplary steps for a backside implant performed to dope an isolated region on the enhanced SOI BOX structure of FIG. 4A for implementing an enhanced SOI BOX structure in accordance with another preferred embodiment; [0016] FIG. 7A is a diagram not to scale illustrating further exemplary steps for implementing silicon-on-insulator (SOI) transistor processing on the enhanced SOI BOX structure of FIG. 6 in accordance with another preferred embodiment; [0017] FIG. 7B is diagram not to scale illustrating further exemplary steps for implementing metal-oxide semiconductor (MOS) processing on the enhanced SOI BOX structure of FIG. 7A in accordance with another preferred embodiment; [0018] FIG. 8 is a diagram not to scale illustrating further exemplary steps for MOS and backside processing on the enhanced SOI BOX structure of FIG. 7B for implementing an enhanced SOI BOX structure in accordance with another preferred embodiment; [0019] FIGS. 9A, 9B, 10, and 11 are diagrams not to scale illustrating exemplary steps for implementing an enhanced SOI BOX structure forming a novel backside anti-fuse (AF) structure in accordance with another preferred embodiment; [0020] FIGS. 12, 13, 14, and 15 are diagrams not to scale illustrating exemplary steps for implementing an enhanced SOI BOX structure for another novel backgate fuse structure for providing a programmable body contact in accordance with another preferred embodiment; and Continue reading... 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