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  Methods of forming semiconductor constructionsUSPTO Application #: 20070093034Title: Methods of forming semiconductor constructions Abstract: The invention includes a method of forming a semiconductor construction. A semiconductor substrate is provided, and a conductive node is formed to be supported by the semiconductor substrate. A first conductive material is formed over the conductive node and shaped as a container. The container has an opening extending therein and an upper surface proximate the opening. The container opening is at least partially filled with an insulative material. A second conductive material is formed over the at least partially filled container opening and physically against the upper surface of the container. The invention also includes semiconductor structures. (end of abstract) Agent: Wells St. John P.s. - Spokane, WA, US Inventors: Cem Basceri, Garo J. Derderian USPTO Applicaton #: 20070093034 - Class: 438396000 (USPTO) Related Patent Categories: Semiconductor Device Manufacturing: Process, Making Passive Device (e.g., Resistor, Capacitor, Etc.), Stacked Capacitor The Patent Description & Claims data below is from USPTO Patent Application 20070093034. Brief Patent Description - Full Patent Description - Patent Application Claims
RELATED PATENT DATA [0001] This patent resulted from a continuation application of U.S. patent application Ser. No. 10/464,231, which was filed Jun. 17, 2003, and which is hereby incorporated by reference; which resulted from a divisional application of U.S. patent application Ser. No. 10/094,581, which was filed Mar. 6, 2002, and which is hereby incorporated by reference. TECHNICAL FIELD [0002] The invention pertains to methods of forming semiconductor constructions, and pertains to the constructions themselves. In particular aspects, the invention pertains to methods of forming electrical contacts and/or methods of forming capacitor constructions. BACKGROUND OF THE INVENTION [0003] One type of semiconductor construction is a metal-insulator-metal (MIM) capacitor construction. A fragment 10 of a semiconductor structure is illustrated in FIG. 1, and such shows an exemplary MIM capacitor construction 20. More specifically, fragment 10 comprises a substrate 12 having a conductively-doped diffusion region 14 therein. Substrate 12 can comprise, for example, monocrystalline silicon. To aid in interpretation of the claims that follow, the terms "semiconductive substrate" and "semiconductor substrate" are defined to mean any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other materials). The term "substrate" refers to any supporting structure, including, but not limited to, the semiconductive substrates described above. [0004] Conductively-doped diffusion region 14 can be doped with one or both of n-type and p-type dopant. [0005] A conductive pedestal 16 is supported by substrate 12, and formed in electrical connection with diffusion region 14. Pedestal 16 can comprise metal and/or conductively doped silicon. In particular aspects, pedestal 16 will comprise, consist essentially of, or consist of conductively-doped silicon such as, for example, conductively-doped polycrystalline silicon. [0006] An insulative mass 18 is formed over substrate 12 and around pedestal 16. Alternatively, pedestal 16 can be considered to extend through mass 18 and to the diffusion region 14 formed within substrate 12. Mass 18 can comprise, for example, borophosphosilicate glass (BPSG). [0007] A first capacitor electrode 22 and barrier 24 extend within an opening in insulative material 18 to electrically contact pedestal 16. First capacitor electrode 22 will comprise a metal in a MIM construction, and can comprise, for example, one or more of platinum, rhodium, ruthenium, titanium, tantalum and tungsten. Barrier layer 24 can comprise, for example, titanium nitride, tantalum nitride, and/or tantalum silicon nitride. [0008] An insulative material 26 is formed over capacitor electrode 22. Material 26 can comprise, for example, one or more of aluminum oxide (Al.sub.2O.sub.3), tantalum pentoxide, barium strontium titanate (BST), lead zirconate titanate (PZT), and/or lead lanthanum zirconate titanate (PLZT). [0009] Barrier layer 24 is provided to alleviate and/or prevent cross-diffusion of materials from dielectric 26 and conductive pedestal 16. Specifically, silicon from a silicon-containing pedestal 16 can migrate through conductive material 22, and oxygen from a dielectric material 26 can also migrate through conductive material 22. [0010] The migration of materials through conductive material 22 is thought to occur along grain boundaries. Specifically, material 22 will generally be formed as a layer, as shown, and will comprise columnar grains extending through the thickness of the layer and defining boundaries 23 between the grains. The boundaries 23 can, as shown, extend across an entirety of the thickness of material 22. Oxygen and silicon are believed to be able to migrate along boundaries 23, and thereby pass through conductive material 22. Barrier layer 24 is provided to block such migration through material 22. [0011] A final component of structure 10 is a second capacitor electrode 28 which is provided over dielectric material 26. Electrode 28 can comprise any of various conductive materials, including, for example, the same conductive materials described above for incorporation into the first capacitor electrode 22. [0012] Capacitor electrode 28 is capacitively separated from first electrode 22 by dielectric material 26. Accordingly, first electrode 22, dielectric material 26 and second electrode 28 together define at least a portion of a capacitor construction. [0013] It would be desirable to develop new methods for alleviating or preventing diffusion through metal layers (such as, for example, the capacitor electrode 22 metal layer of FIG. 1), and to incorporate such methods into formation of electrical contacts and/or capacitor constructions. SUMMARY OF THE INVENTION [0014] In one aspect, the invention encompasses a method of forming an electrical contact. A semiconductor substrate is provided, and a conductive node is formed to be supported by the semiconductor substrate. A first conductive material is formed over the conductive node and shaped as a container. The container has an opening extending therein and an upper surface proximate the opening. The container opening is at least partially filled with an insulative material. A second conductive material is formed over the at least partially filled container opening and physically against the upper surface of the container. [0015] In one aspect, the invention encompasses a capacitor construction. The construction includes a semiconductor substrate comprising a silicon-containing surface. A first conductive material is over the silicon-containing surface and shaped as an upwardly-opening container. The container has an upper surface proximate the opening. A first insulative material is within the container opening. A second conductor material is over the container opening and physically against the upper surface of the container. A second insulative material is over the second conductor material. A third conductive material is over the second insulative material. The third conductive material is capacitively separated from the second conductive material by the second insulative material. [0016] In one aspect, the invention encompasses a semiconductor construction. The construction includes a semiconductor substrate, and a silicon-containing electrically conductive node supported by the semiconductor substrate. A first conductive layer is physically against a surface of the conductive node and shaped as a container. The first conductive layer has a first thickness and has grain boundaries extending across the first thickness. A second conductive layer is over the container and physically against the upper surface of the container. The second conductive layer comprises a second thickness and has grain boundaries extending across the second thickness. BRIEF DESCRIPTION OF THE DRAWINGS [0017] Preferred embodiments of the invention are described below with reference to the following accompanying drawings. [0018] FIG. 1 is a diagrammatic, cross-sectional view of a fragment of a prior art semiconductor construction, illustrating a metal-insulator-metal capacitor construction. [0019] FIG. 2 is a diagrammatic, fragmentary, cross-sectional view of a semiconductor construction illustrating a preliminary stage of a method of a particular aspect of the present invention. Continue reading... Full patent description for Methods of forming semiconductor constructions Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Methods of forming semiconductor constructions patent application. ###  How KEYWORD MONITOR works... a FREE service from FreshPatents1. Sign up (takes 30 seconds). 2. Fill in the keywords to be monitored. 3. Each week you receive an email with patent applications related to your keywords. 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