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  Methods of forming capacitors for semiconductor memory devices and resulting semiconductor memory devicesUSPTO Application #: 20080026538Title: Methods of forming capacitors for semiconductor memory devices and resulting semiconductor memory devices Abstract: Methods of forming capacitors include forming a first mold layer and a second mold layer on a substrate, forming storage electrodes through the mold layers, the storage electrodes arranged in rows extending in a first direction and spaced apart from adjacent storage electrodes along the first direction by a first interval. The storage electrodes are spaced apart from adjacent storage electrodes along a second direction oblique to the first direction by a second interval smaller than the first interval. First and second sacrificial layers are formed on the storage electrodes layer partially filling up a gap between adjacent storage electrodes along the first direction and filling up a gap between the adjacent storage electrodes along the second direction. Sacrificial spacers may be formed on sidewalls of the storage electrodes by etching the sacrificial layers. The second mold layer may be etched using the sacrificial spacers as etching masks to define a plurality of stabilizing structures. Resulting devices are also disclosed. (end of abstract) Agent: Myers Bigel Sibley & Sajovec - Raleigh, NC, US Inventors: Ju Bum Lee, Shin-Hye Kim USPTO Applicaton #: 20080026538 - Class: 438386000 (USPTO) Related Patent Categories: Semiconductor Device Manufacturing: Process, Making Passive Device (e.g., Resistor, Capacitor, Etc.), Trench Capacitor The Patent Description & Claims data below is from USPTO Patent Application 20080026538. Brief Patent Description - Full Patent Description - Patent Application Claims
CROSS REFERENCE TO RELATED APPLICATION [0001] This application claims priority to and is a divisional of parent application Ser. No. 11/195,086, filed Aug. 2, 2005, which claims the benefit from Korean Patent Application No. 2004-64250 filed on Aug. 16, 2004, the disclosure of which is incorporated herein by reference in its entirety. FIELD OF THE INVENTION [0002] The present invention relates to methods of forming capacitors. More particularly, the present invention relates to methods of forming capacitors for semiconductor devices. BACKGROUND [0003] Semiconductor memory devices such as dynamic random access memory (DRAM) devices may be programmable and erasable, such that binary data may be repeatedly stored in and/or read from the semiconductor devices. A typical cell of a semiconductor memory device may include one transistor and one capacitor. The capacitor may have a storage electrode, a dielectric layer and a plate electrode. To increase the ability of a semiconductor memory device to store electric charge (which is representative of data stored by the device), the capacitance of the capacitor may be increased. [0004] Recently, the degree of integration of DRAM devices has reached the gigabyte scale, which may require a corresponding decrease in the cell area of DRAM devices. In order to increase the density of DRAM devices formed on a single substrate, various alternative capacitor geometries have been investigated. For example, to save space on a semiconductor substrate, capacitors have been designed in which the opposing plates of the capacitor extend in a direction perpendicular to the semiconductor substrate instead of parallel to the substrate. Accordingly, capacitors having various structures such as a tube-shaped structure, a cylindrical structure and/or a mesh-shaped structure have been proposed in an attempt to form capacitors having a desired capacitance and area. When DRAM devices have a critical dimension of below about 0.11 .mu.m, the cell area of the DRAM device is also drastically reduced, which means that in order to have a desired capacitance, the capacitor may have a very large aspect ratio (i.e. a very large ratio of height to width). When capacitors in a DRAM device have a considerably large aspect ratio, adjacent capacitors may become tilted toward each other or even fall down, which may cause an electrical short between adjacent capacitors. Such a condition is known as a 2-bit failure of capacitors. [0005] FIG. 1 is a cross-sectional view illustrating storage electrodes 14 of conventional cylindrical capacitors. Referring to FIG. 1, a conventional cylindrical capacitor 1 includes a storage electrode 14 contacting a contact pad 12 formed on a semiconductor substrate 10. The storage electrode 14 of the capacitor may be electrically connected through the contact pad 12 to a metal oxide semiconductor (MOS) transistor (not shown) formed on the semiconductor substrate 10. [0006] To increase the capacitance of the capacitor, the height of the storage electrode 14 may be increased. However, when the height of the storage electrode 14 becomes large, the storage electrode 14 may lean on an adjacent storage electrode 14, or adjacent storage electrodes 14 may fall down toward each other as shown by the dotted lines in FIG. 1. This 2-bit failure between adjacent storage electrodes 14 may cause an electrical failure of the semiconductor device. [0007] In order to reduce the likelihood of a failure such as a 2-bit failure described above, a stabilizing member having a mesh structure may be formed to enclose the storage electrode of a capacitor. Adjacent stabilizing members may be connected to each other in an attempt to prevent the storage electrodes from falling down or leaning on each other. [0008] In forming the stabilizing member, a first mold layer, a second mold layer and a third mold layer may be sequentially formed on a semiconductor substrate. The mold layers may be selectively etched to form holes therethrough which expose a contact region of the semiconductor substrate. After a conductive layer and a sacrificial layer are formed to fill the holes, the conductive layer and the sacrificial layer may be partially removed by a chemical mechanical polishing (CMP) process until the third mold layer is exposed, thereby forming storage electrodes in the holes. When the third mold layer is removed, the second mold layer and upper portions of the storage electrodes may be exposed. A silicon oxide layer may be formed on the second mold layer and the exposed portions of the storage electrodes. Then, the silicon oxide layer may be anisotropically etched to form spacers on sidewalls of the storage electrodes. Using the spacers as etching masks, the second mold layer may be partially etched to thereby form stabilizing members enclosing the upper portions of the storage electrodes. [0009] However, the silicon oxide layer used to form the spacers may have poor step coverage. In addition, the surface profile of the mold layers may cause a loading effect on the silicon oxide layer. As a result, the stabilizing members may not be uniformly formed on the sidewalls of the storage electrodes. Additionally, the CMP process used for forming the storage electrodes may cause a dishing effect to occur, which may cause the storage electrodes to have non-uniform heights. The foregoing problems may cause the spacers to be non-uniform. Thus, forming uniform stabilizing members may be difficult. SUMMARY [0010] Some methods of forming capacitors according to embodiments of the invention include forming a first mold layer and a second mold layer on a substrate, forming storage electrodes arranged in a regular two dimensional configuration through the second mold layer and the first mold layer, upper portions of the storage electrodes being protruded from the second mold layer, forming a first sacrificial layer on the storage electrodes and the second mold layer, the sacrificial layer partially filling up a gap between adjacent storage electrodes along a first direction and filling up a gap between the adjacent storage electrodes along a second direction, a first recess being formed between the adjacent storage electrodes along the first direction, forming sacrificial spacers on sidewalls of the storage electrodes by etching the first sacrificial layer, the sacrificial spacers defining an opening exposing the second mold layer between the adjacent storage electrodes along the first direction, etching the exposed second mold layer to expose the first mold layer, removing the first mold layer and the sacrificial spacers, and forming a dielectric layer and a plate electrode on the storage electrodes. [0011] Methods according to some embodiments of the invention further include forming a second sacrificial layer on the first sacrificial layer, wherein forming sacrificial spacers on the sidewalls of the storage electrode includes etching the second and the first sacrificial layers to define an opening exposing the second mold layer. Forming the second sacrificial layer may further include partially filling the first recess to thereby form a second recess. [0012] In some embodiments of the invention, the first sacrificial layer may be formed by a chemical vapor deposition process using an ozone gas and a tetraethyl orthosilicate gas. The second sacrificial layer may be formed by a plasma enhanced chemical vapor deposition process using an oxygen gas and a tetraethyl orthosilicate gas. [0013] In some embodiments according to the invention, forming the storage electrodes includes forming a third mold layer on the second mold layer, forming first openings exposing the contact structures through the third mold layer, the second mold layer and the first mold layer, forming a conductive layer on the contact structures, sidewalls of the first openings and the third mold layer, forming a third sacrificial layer on the conductive layer, removing portions of the third sacrificial layer and the conductive layer until the third mold layer is exposed, to thereby form storage electrodes and sacrificial layer patterns within the storage electrodes, and exposing the upper portions of the storage electrodes by removing the third mold layer and upper portions of the sacrificial layer patterns. [0014] In some embodiments, the first mold layer and the third mold layer pattern include silicon oxide, and the second mold layer includes silicon nitride. In further embodiments, the third sacrificial layer is formed of the same material as the third mold layer. [0015] According to some embodiments of the invention, forming the first openings further includes forming a mask pattern on the third mold layer, and anisotropically etching the third mold layer, the second mold layer and the first mold layer using the mask pattern as an etching mask. The mask pattern may include polysilicon. [0016] In further embodiments, forming the storage electrodes includes forming a third mold layer on the second mold layer, forming a polishing stop layer on the third mold layer, forming first openings exposing the contact structures through the polishing stop layer, the third mold layer, the second mold layer and the first mold layer, forming a conductive layer on the contact structures, sidewalls of the first openings and the polishing stop layer, forming a third sacrificial layer on the conductive layer to fill up the first openings, removing the third sacrificial layer and the conductive layer until the polishing stop layer is exposed to thereby form storage electrodes and sacrificial layer patterns in the storage electrodes, and exposing upper portions of the storage electrodes by removing the polishing stop layer, the third mold layer and upper portions of the sacrificial layer patterns. [0017] In some embodiments, the polishing stop layer comprises silicon nitride. Some embodiments according to the invention further include forming a buffer oxide layer on the polishing stop layer, forming a mask pattern on the buffer oxide layer, and anisotropically etching the buffer oxide layer, the polishing stop layer, the third mold layer, the second mold layer and the first mold layer using the mask pattern as an etching mask. [0018] Methods according to further embodiments of the invention include forming a first mold layer and a second mold layer on a substrate where contact structures are formed, forming storage electrodes through the second mold layer and the first mold layer, the storage electrodes arranged in a plurality of rows extending in a first direction, the storage electrodes spaced apart from adjacent storage electrodes along the first direction by a first interval, and upper portions of the storage electrodes being protruded from the second mold layer, wherein successive rows of storage electrodes are offset from one another such that a storage electrode in one row is arranged in the first direction between two storage electrodes in a neighboring row. The first direction may correspond to a bit line structure or a word line structure of a semiconductor memory device. [0019] In some embodiments, a storage electrode in one row is arranged in the first direction about half way between two adjacent storage electrodes in a neighboring row. The storage electrodes may be spaced apart from adjacent storage electrodes along a second direction oblique to the first direction by a second interval smaller than the first interval. [0020] In some embodiments, methods according to the invention may further include forming a first sacrificial layer on the storage electrodes and the second mold layer, the sacrificial layer partially filling up a gap between adjacent storage electrodes along the first direction, thereby forming a first recess between adjacent storage electrodes along the first direction, and filling up a gap between the adjacent storage electrodes along the second direction; forming sacrificial spacers on sidewalls of the storage electrodes, the sacrificial spacers defining an opening exposing the second mold layer between the adjacent storage electrodes along the first direction, etching the exposed second mold layer to expose the first mold layer, removing the first mold layer and the sacrificial spacers, and forming a dielectric layer and a plate electrode on the storage electrodes. Continue reading... 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