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  Methods of forming a semiconductor device including buried bit linesUSPTO Application #: 20070295995Title: Methods of forming a semiconductor device including buried bit lines Abstract: A method of forming a buried interconnection includes removing a semiconductor substrate to form a groove in the semiconductor substrate. A metal layer is formed on inner walls of the groove using an electroless deposition technique. A silicidation process is applied to the substrate having the metal layer, thereby forming a metal silicide layer on the inner walls of the groove. (end of abstract)
Agent: Marger Johnson & Mccollom, P.C. - Portland, OR, US Inventors: Jong-Ho Yun, Byung-Hee Kim, Dae-Yong Kim, Hyun-Su Kim, Eun-Ji Jung, Eun-Ok Lee USPTO Applicaton #: 20070295995 - Class: 257202 (USPTO) The Patent Description & Claims data below is from USPTO Patent Application 20070295995. Brief Patent Description - Full Patent Description - Patent Application Claims
CROSS-REFERENCE TO RELATED APPLICATION [0001]This application claims the benefit of foreign priority to Korean Patent Application No. 10-2006-52073, filed Jun. 9, 2006, the disclosure of which is incorporated herein by reference in its entirety. BACKGROUND [0002]1. Field of Invention [0003]Embodiments of the present invention relate generally to methods of forming semiconductor devices including a buried interconnection line and, more particularly, to methods of forming semiconductor devices including a buried bit line. [0004]2. Description of the Related Art [0005]As semiconductor devices become more highly integrated, transistors included therein shrink in size. Shrinkage of the transistors leads to a reduction of active regions, in size, where the transistors are formed. Accordingly, the transistors of highly integrated semiconductor devices may suffer from a short channel effect and/or a narrow width effect. [0006]A three dimensional transistor such as a vertical transistor has been proposed instead of a conventional planar transistor in order to increase a channel length and/or a channel width in a limited area. Vertical transistors may be very useful to semiconductor memory devices such as dynamic random access memory (DRAM) devices. In a conventional DRAM device employing the vertical transistor as a memory cell transistor, a bit line of the DRAM device may be formed using an ion implantation technique. In this case, there may be a limitation in reducing an electrical resistance of the bit line. Therefore, a method of forming a buried bit line has been proposed to decrease the electrical resistance of the bit line. [0007]In general, buried bit lines may be formed by etching a semiconductor substrate to form a groove and forming a conductive layer on an entire surface of the semiconductor substrate with the groove using a chemical vapor deposition (CVD) technique. The conductive layer may then be etched back to form a pair of separate bit lines on both sidewalls of the groove respectively. The thickness of the conductive layer should be increased in order to decrease the electrical resistance of the bit lines. However, as the integration density of the semiconductor device increases, the width of the groove may be reduced. In this case, there is a limitation in increasing the thickness of the conductive layer. In the event that the thickness of the conductive layer increases, the conductive layer may be formed to have overhangs on upper corners of the groove and the overhangs may be in contact with each other. Therefore, the conductive layer on the bottom surface of the groove may not be removed while the conductive layer is etched back to form the bit lines. This may be due to the presence of the overhangs. As a result, it may be difficult to form a pair of low resistive bit lines, which are electrically isolated from each other, in the narrow groove. SUMMARY [0008]An embodiment exemplarily described herein can be generally characterized as a method of forming a semiconductor device that includes removing a portion of a semiconductor substrate to define a first groove therein, the first groove comprising a sidewall and a bottom surface; and forming a buried interconnection within the first groove. The buried interconnection may be formed, for example, by applying an electroless deposition process to form a metal layer on the sidewall and the bottom surface of the first groove; and reacting the semiconductor substrate and the metal layer to form a metal silicide layer on the sidewall and the bottom surface of the first groove. [0009]Another embodiment exemplarily described herein can be generally characterized as a method of forming a semiconductor device that includes removing a first portion of a semiconductor substrate to form a channel structure; forming a gate pattern on a sidewall of the channel structure; removing a second portion of the semiconductor substrate adjacent to the sidewall of the channel structure to form a bit line groove having a sidewall and a bottom surface; and forming a bit line within the bit line groove. The first portion of the semiconductor substrate may extend from a top surface of the semiconductor substrate to a level below the top surface of the semiconductor substrate and the sidewall of the channel structure may extend from the level below the top surface of the semiconductor substrate toward the top surface of the semiconductor substrate. The bit line may be formed, for example, by applying an electroless deposition process to form a metal layer on the sidewall and the bottom surface of the bit line groove; and reacting the semiconductor substrate and the metal layer to form a metal silicide layer on the sidewall and the bottom surface of the bit line groove. [0010]Yet another embodiment exemplarily described herein can be generally characterized as a method of fabricating a semiconductor device that includes removing a first portion of a semiconductor substrate to form a channel structure; forming a gate insulation layer on a sidewall of the channel structure; forming a gate pattern on a sidewall of the gate insulation layer; removing a second portion of the semiconductor substrate adjacent to the channel structure to form a bit line groove having a sidewall and a bottom surface; forming a bit line within the bit line groove; and forming a word line electrically connected to the gate pattern. The first portion of the semiconductor substrate may extend from a top surface of the semiconductor substrate to a level below the top surface of the semiconductor substrate and the sidewall of the channel structure may extend from the level below the top surface of the semiconductor substrate toward the top surface of the semiconductor substrate. The bit line may be formed, for example, by applying an electroless deposition process to form a metal layer on the sidewall and the bottom surface of the bit line groove; reacting the semiconductor substrate and the metal layer to form a metal silicide layer on the sidewall and the bottom surface of the bit line groove; and removing a portion of the metal silicide layer on the bottom surface of the bit line groove. [0011]Still another embodiment exemplarily described herein can be generally characterized as a semiconductor device that includes a semiconductor substrate having an upper surface; a plurality of channel structures on the substrate, wherein each channel structure has a sidewall extending from the upper surface of the semiconductor substrate to a height above the upper surface of the semiconductor substrate; a plurality of gate patterns formed on sidewalls of corresponding ones of the plurality of channel structures; a bit line groove defined between sidewalls of adjacent ones of the plurality of channel structures, the bit line groove having opposing sidewalls; and a plurality of bit lines formed on corresponding ones of the opposing sidewalls, wherein the plurality of bit lines are electrically isolated from each other. BRIEF DESCRIPTION OF THE DRAWINGS [0012]The above and other features and advantages of the exemplary embodiments of the present invention will become more apparent to those of ordinary skill in the art by describing in detail exemplary embodiments thereof with reference to the attached drawings in which: [0013]FIG. 1 is a perspective view illustrating a semiconductor device according to one embodiment; [0014]FIGS. 2A and 2B are vertical sectional views taken along a word line direction and a bit line direction of FIG. 1; [0015]FIGS. 3 to 8 are vertical sectional views taken along a word line direction of FIG. 1 to exemplarily illustrate methods of forming a semiconductor device according to one embodiment; and [0016]FIGS. 9 to 11 are vertical sectional views taken along a word line direction of FIG. 1 to exemplarily illustrate methods of forming a semiconductor device according to another embodiment. DETAILED DESCRIPTION [0017]Exemplary embodiments of present invention will now be described more fully hereinafter with reference to the accompanying drawings. These exemplary embodiments may, however, be realized in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. [0018]It will be understood that when a material layer such as a conductive layer, a semiconductor layer or an insulation layer is referred to as being "on" another material layer or substrate, it can be directly on the other material layer or substrate or intervening layers may be present therebetween. [0019]It will be understood that, although the terms fist, second, third, etc. may be used herein to describe various material layers or process steps, these layer or process steps should not be limited by these terms. These terms are only used to distinguish a specific material layer or process step from another material layer or process step. Continue reading... Full patent description for Methods of forming a semiconductor device including buried bit lines Brief Patent Description - Full Patent Description - Patent Application Claims Click on the above for other options relating to this Methods of forming a semiconductor device including buried bit lines patent application. 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